Lines Matching refs:ah
33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) in ath9k_hw_set_clockrate() argument
42 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_clockrate()
43 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_clockrate()
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) in ath9k_hw_set_clockrate()
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) in ath9k_hw_mac_to_clks() argument
72 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_mac_to_clks()
77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) in ath9k_hw_wait() argument
84 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
90 ath_dbg(ath9k_hw_common(ah), ANY, in ath9k_hw_wait()
92 timeout, reg, REG_READ(ah, reg), mask, val); in ath9k_hw_wait()
98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_synth_delay() argument
111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, in ath9k_hw_write_array() argument
116 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_write_array()
118 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
122 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_write_array()
125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) in ath9k_hw_read_array() argument
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); in ath9k_hw_read_array()
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); in ath9k_hw_read_array()
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); in ath9k_hw_read_array()
167 u16 ath9k_hw_computetxtime(struct ath_hw *ah, in ath9k_hw_computetxtime() argument
186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
193 } else if (ah->curchan && in ath9k_hw_computetxtime()
194 IS_CHAN_HALF_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
210 ath_err(ath9k_hw_common(ah), in ath9k_hw_computetxtime()
220 void ath9k_hw_get_channel_centers(struct ath_hw *ah, in ath9k_hw_get_channel_centers() argument
253 static void ath9k_hw_read_revisions(struct ath_hw *ah) in ath9k_hw_read_revisions() argument
257 if (ah->get_mac_revision) in ath9k_hw_read_revisions()
258 ah->hw_version.macRev = ah->get_mac_revision(); in ath9k_hw_read_revisions()
260 switch (ah->hw_version.devid) { in ath9k_hw_read_revisions()
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100; in ath9k_hw_read_revisions()
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330; in ath9k_hw_read_revisions()
266 if (!ah->get_mac_revision) { in ath9k_hw_read_revisions()
267 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
272 ah->hw_version.macVersion = AR_SREV_VERSION_9340; in ath9k_hw_read_revisions()
275 ah->hw_version.macVersion = AR_SREV_VERSION_9550; in ath9k_hw_read_revisions()
278 ah->hw_version.macVersion = AR_SREV_VERSION_9531; in ath9k_hw_read_revisions()
281 ah->hw_version.macVersion = AR_SREV_VERSION_9561; in ath9k_hw_read_revisions()
285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; in ath9k_hw_read_revisions()
288 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
289 ah->hw_version.macVersion = in ath9k_hw_read_revisions()
291 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
293 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_read_revisions()
294 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
296 ah->is_pciexpress = (val & in ath9k_hw_read_revisions()
299 if (!AR_SREV_9100(ah)) in ath9k_hw_read_revisions()
300 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); in ath9k_hw_read_revisions()
302 ah->hw_version.macRev = val & AR_SREV_REVISION; in ath9k_hw_read_revisions()
304 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) in ath9k_hw_read_revisions()
305 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
313 static void ath9k_hw_disablepcie(struct ath_hw *ah) in ath9k_hw_disablepcie() argument
315 if (!AR_SREV_5416(ah)) in ath9k_hw_disablepcie()
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
332 static bool ath9k_hw_chip_test(struct ath_hw *ah) in ath9k_hw_chip_test() argument
334 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_chip_test()
342 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_chip_test()
352 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
355 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
356 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
366 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
367 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
375 REG_WRITE(ah, regAddr[i], regHold[i]); in ath9k_hw_chip_test()
382 static void ath9k_hw_init_config(struct ath_hw *ah) in ath9k_hw_init_config() argument
384 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_config()
386 ah->config.dma_beacon_response_time = 1; in ath9k_hw_init_config()
387 ah->config.sw_beacon_response_time = 6; in ath9k_hw_init_config()
388 ah->config.cwm_ignore_extcca = false; in ath9k_hw_init_config()
389 ah->config.analog_shiftreg = 1; in ath9k_hw_init_config()
391 ah->config.rx_intr_mitigation = true; in ath9k_hw_init_config()
393 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_config()
394 ah->config.rimt_last = 500; in ath9k_hw_init_config()
395 ah->config.rimt_first = 2000; in ath9k_hw_init_config()
397 ah->config.rimt_last = 250; in ath9k_hw_init_config()
398 ah->config.rimt_first = 700; in ath9k_hw_init_config()
401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_init_config()
402 ah->config.pll_pwrsave = 7; in ath9k_hw_init_config()
421 ah->config.serialize_regmode = SER_REG_MODE_AUTO; in ath9k_hw_init_config()
423 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { in ath9k_hw_init_config()
424 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || in ath9k_hw_init_config()
425 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && in ath9k_hw_init_config()
426 !ah->is_pciexpress)) { in ath9k_hw_init_config()
427 ah->config.serialize_regmode = SER_REG_MODE_ON; in ath9k_hw_init_config()
429 ah->config.serialize_regmode = SER_REG_MODE_OFF; in ath9k_hw_init_config()
434 ah->config.serialize_regmode); in ath9k_hw_init_config()
436 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_config()
437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; in ath9k_hw_init_config()
439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; in ath9k_hw_init_config()
442 static void ath9k_hw_init_defaults(struct ath_hw *ah) in ath9k_hw_init_defaults() argument
444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_init_defaults()
449 ah->hw_version.magic = AR5416_MAGIC; in ath9k_hw_init_defaults()
450 ah->hw_version.subvendorid = 0; in ath9k_hw_init_defaults()
452 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | in ath9k_hw_init_defaults()
454 if (AR_SREV_9100(ah)) in ath9k_hw_init_defaults()
455 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; in ath9k_hw_init_defaults()
457 ah->slottime = ATH9K_SLOT_TIME_9; in ath9k_hw_init_defaults()
458 ah->globaltxtimeout = (u32) -1; in ath9k_hw_init_defaults()
459 ah->power_mode = ATH9K_PM_UNDEFINED; in ath9k_hw_init_defaults()
460 ah->htc_reset_init = true; in ath9k_hw_init_defaults()
462 ah->tpc_enabled = false; in ath9k_hw_init_defaults()
464 ah->ani_function = ATH9K_ANI_ALL; in ath9k_hw_init_defaults()
465 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_init_defaults()
466 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; in ath9k_hw_init_defaults()
468 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_defaults()
469 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
471 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
474 static int ath9k_hw_init_macaddr(struct ath_hw *ah) in ath9k_hw_init_macaddr() argument
476 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_macaddr()
484 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); in ath9k_hw_init_macaddr()
503 static int ath9k_hw_post_init(struct ath_hw *ah) in ath9k_hw_post_init() argument
505 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_post_init()
509 if (!ath9k_hw_chip_test(ah)) in ath9k_hw_post_init()
513 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
514 ecode = ar9002_hw_rf_claim(ah); in ath9k_hw_post_init()
519 ecode = ath9k_hw_eeprom_init(ah); in ath9k_hw_post_init()
523 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", in ath9k_hw_post_init()
524 ah->eep_ops->get_eeprom_ver(ah), in ath9k_hw_post_init()
525 ah->eep_ops->get_eeprom_rev(ah)); in ath9k_hw_post_init()
527 ath9k_hw_ani_init(ah); in ath9k_hw_post_init()
533 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
534 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_post_init()
536 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; in ath9k_hw_post_init()
537 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; in ath9k_hw_post_init()
544 static int ath9k_hw_attach_ops(struct ath_hw *ah) in ath9k_hw_attach_ops() argument
546 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_attach_ops()
547 return ar9002_hw_attach_ops(ah); in ath9k_hw_attach_ops()
549 ar9003_hw_attach_ops(ah); in ath9k_hw_attach_ops()
554 static int __ath9k_hw_init(struct ath_hw *ah) in __ath9k_hw_init() argument
556 struct ath_common *common = ath9k_hw_common(ah); in __ath9k_hw_init()
559 ath9k_hw_read_revisions(ah); in __ath9k_hw_init()
561 switch (ah->hw_version.macVersion) { in __ath9k_hw_init()
583 ah->hw_version.macVersion, ah->hw_version.macRev); in __ath9k_hw_init()
592 if (AR_SREV_9300_20_OR_LATER(ah)) { in __ath9k_hw_init()
593 ah->WARegVal = REG_READ(ah, AR_WA); in __ath9k_hw_init()
594 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | in __ath9k_hw_init()
598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in __ath9k_hw_init()
603 if (AR_SREV_9565(ah)) { in __ath9k_hw_init()
604 ah->WARegVal |= AR_WA_BIT22; in __ath9k_hw_init()
605 REG_WRITE(ah, AR_WA, ah->WARegVal); in __ath9k_hw_init()
608 ath9k_hw_init_defaults(ah); in __ath9k_hw_init()
609 ath9k_hw_init_config(ah); in __ath9k_hw_init()
611 r = ath9k_hw_attach_ops(ah); in __ath9k_hw_init()
615 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { in __ath9k_hw_init()
620 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || in __ath9k_hw_init()
621 AR_SREV_9330(ah) || AR_SREV_9550(ah)) in __ath9k_hw_init()
622 ah->is_pciexpress = false; in __ath9k_hw_init()
624 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in __ath9k_hw_init()
625 ath9k_hw_init_cal_settings(ah); in __ath9k_hw_init()
627 if (!ah->is_pciexpress) in __ath9k_hw_init()
628 ath9k_hw_disablepcie(ah); in __ath9k_hw_init()
630 r = ath9k_hw_post_init(ah); in __ath9k_hw_init()
634 ath9k_hw_init_mode_gain_regs(ah); in __ath9k_hw_init()
635 r = ath9k_hw_fill_cap_info(ah); in __ath9k_hw_init()
639 r = ath9k_hw_init_macaddr(ah); in __ath9k_hw_init()
645 ath9k_hw_init_hang_checks(ah); in __ath9k_hw_init()
652 int ath9k_hw_init(struct ath_hw *ah) in ath9k_hw_init() argument
655 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init()
658 switch (ah->hw_version.devid) { in ath9k_hw_init()
685 ah->hw_version.devid); in ath9k_hw_init()
689 ret = __ath9k_hw_init(ah); in ath9k_hw_init()
697 ath_dynack_init(ah); in ath9k_hw_init()
703 static void ath9k_hw_init_qos(struct ath_hw *ah) in ath9k_hw_init_qos() argument
705 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_qos()
707 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
708 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
710 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
715 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ath9k_hw_init_qos()
716 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
717 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
718 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
719 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
721 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_qos()
724 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) in ar9003_get_pll_sqsum_dvc() argument
726 struct ath_common *common = ath9k_hw_common(ah); in ar9003_get_pll_sqsum_dvc()
729 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
731 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
733 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
745 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; in ar9003_get_pll_sqsum_dvc()
749 static void ath9k_hw_init_pll(struct ath_hw *ah, in ath9k_hw_init_pll() argument
754 pll = ath9k_hw_compute_pll_control(ah, chan); in ath9k_hw_init_pll()
756 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_init_pll()
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
783 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
786 } else if (AR_SREV_9330(ah)) { in ath9k_hw_init_pll()
789 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
800 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); in ath9k_hw_init_pll()
803 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, in ath9k_hw_init_pll()
806 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
811 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); in ath9k_hw_init_pll()
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); in ath9k_hw_init_pll()
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); in ath9k_hw_init_pll()
818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
820 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_pll()
821 AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
824 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
828 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); in ath9k_hw_init_pll()
831 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
832 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
842 if (AR_SREV_9340(ah)) { in ath9k_hw_init_pll()
848 pll2_divfrac = (AR_SREV_9531(ah) || in ath9k_hw_init_pll()
849 AR_SREV_9561(ah)) ? in ath9k_hw_init_pll()
855 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
856 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ath9k_hw_init_pll()
860 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
863 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
867 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
868 if (AR_SREV_9340(ah)) in ath9k_hw_init_pll()
874 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
881 if (AR_SREV_9531(ah)) in ath9k_hw_init_pll()
889 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
891 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ath9k_hw_init_pll()
892 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
893 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); in ath9k_hw_init_pll()
895 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
896 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); in ath9k_hw_init_pll()
901 if (AR_SREV_9565(ah)) in ath9k_hw_init_pll()
903 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ath9k_hw_init_pll()
905 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ath9k_hw_init_pll()
906 AR_SREV_9550(ah)) in ath9k_hw_init_pll()
910 if (AR_SREV_9271(ah)) { in ath9k_hw_init_pll()
912 REG_WRITE(ah, 0x50040, 0x304); in ath9k_hw_init_pll()
917 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); in ath9k_hw_init_pll()
920 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, in ath9k_hw_init_interrupt_masks() argument
930 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_interrupt_masks()
931 AR_SREV_9561(ah)) in ath9k_hw_init_interrupt_masks()
934 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
936 if (ah->config.rx_intr_mitigation) in ath9k_hw_init_interrupt_masks()
942 if (ah->config.rx_intr_mitigation) in ath9k_hw_init_interrupt_masks()
948 if (ah->config.tx_intr_mitigation) in ath9k_hw_init_interrupt_masks()
953 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_interrupt_masks()
955 REG_WRITE(ah, AR_IMR, imr_reg); in ath9k_hw_init_interrupt_masks()
956 ah->imrs2_reg |= AR_IMR_S2_GTT; in ath9k_hw_init_interrupt_masks()
957 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_init_interrupt_masks()
959 if (!AR_SREV_9100(ah)) { in ath9k_hw_init_interrupt_masks()
960 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
961 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); in ath9k_hw_init_interrupt_masks()
962 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
965 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_interrupt_masks()
967 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
968 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
969 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
970 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
971 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
975 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) in ath9k_hw_set_sifs_time() argument
977 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); in ath9k_hw_set_sifs_time()
979 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); in ath9k_hw_set_sifs_time()
982 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) in ath9k_hw_setslottime() argument
984 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_setslottime()
986 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); in ath9k_hw_setslottime()
989 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_ack_timeout() argument
991 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_ack_timeout()
993 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); in ath9k_hw_set_ack_timeout()
996 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_cts_timeout() argument
998 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_cts_timeout()
1000 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); in ath9k_hw_set_cts_timeout()
1003 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) in ath9k_hw_set_global_txtimeout() argument
1006 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", in ath9k_hw_set_global_txtimeout()
1008 ah->globaltxtimeout = (u32) -1; in ath9k_hw_set_global_txtimeout()
1011 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); in ath9k_hw_set_global_txtimeout()
1012 ah->globaltxtimeout = tu; in ath9k_hw_set_global_txtimeout()
1017 void ath9k_hw_init_global_settings(struct ath_hw *ah) in ath9k_hw_init_global_settings() argument
1019 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_global_settings()
1020 const struct ath9k_channel *chan = ah->curchan; in ath9k_hw_init_global_settings()
1027 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", in ath9k_hw_init_global_settings()
1028 ah->misc_mode); in ath9k_hw_init_global_settings()
1033 if (ah->misc_mode != 0) in ath9k_hw_init_global_settings()
1034 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); in ath9k_hw_init_global_settings()
1036 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1051 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1061 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1068 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_init_global_settings()
1072 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ in ath9k_hw_init_global_settings()
1074 reg = REG_READ(ah, AR_USEC); in ath9k_hw_init_global_settings()
1079 slottime = ah->slottime; in ath9k_hw_init_global_settings()
1083 slottime += 3 * ah->coverage_class; in ath9k_hw_init_global_settings()
1096 acktimeout += 64 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1097 ctstimeout += 48 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1100 if (ah->dynack.enabled) { in ath9k_hw_init_global_settings()
1101 acktimeout = ah->dynack.ackto; in ath9k_hw_init_global_settings()
1105 ah->dynack.ackto = acktimeout; in ath9k_hw_init_global_settings()
1108 ath9k_hw_set_sifs_time(ah, sifstime); in ath9k_hw_init_global_settings()
1109 ath9k_hw_setslottime(ah, slottime); in ath9k_hw_init_global_settings()
1110 ath9k_hw_set_ack_timeout(ah, acktimeout); in ath9k_hw_init_global_settings()
1111 ath9k_hw_set_cts_timeout(ah, ctstimeout); in ath9k_hw_init_global_settings()
1112 if (ah->globaltxtimeout != (u32) -1) in ath9k_hw_init_global_settings()
1113 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); in ath9k_hw_init_global_settings()
1115 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); in ath9k_hw_init_global_settings()
1116 REG_RMW(ah, AR_USEC, in ath9k_hw_init_global_settings()
1125 void ath9k_hw_deinit(struct ath_hw *ah) in ath9k_hw_deinit() argument
1127 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_deinit()
1132 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); in ath9k_hw_deinit()
1156 static inline void ath9k_hw_set_dma(struct ath_hw *ah) in ath9k_hw_set_dma() argument
1158 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_dma()
1161 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1166 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1167 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1172 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1174 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1181 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1182 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); in ath9k_hw_set_dma()
1184 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1189 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1194 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1196 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_dma()
1197 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); in ath9k_hw_set_dma()
1198 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); in ath9k_hw_set_dma()
1200 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - in ath9k_hw_set_dma()
1201 ah->caps.rx_status_len); in ath9k_hw_set_dma()
1208 if (AR_SREV_9285(ah)) { in ath9k_hw_set_dma()
1214 } else if (AR_SREV_9340_13_OR_LATER(ah)) { in ath9k_hw_set_dma()
1221 if (!AR_SREV_9271(ah)) in ath9k_hw_set_dma()
1222 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); in ath9k_hw_set_dma()
1224 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1226 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1227 ath9k_hw_reset_txstatus_ring(ah); in ath9k_hw_set_dma()
1230 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) in ath9k_hw_set_operating_mode() argument
1235 ENABLE_REG_RMW_BUFFER(ah); in ath9k_hw_set_operating_mode()
1238 if (!AR_SREV_9340_13(ah)) { in ath9k_hw_set_operating_mode()
1240 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1250 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1253 if (!ah->is_monitoring) in ath9k_hw_set_operating_mode()
1257 REG_RMW(ah, AR_STA_ID1, set, mask); in ath9k_hw_set_operating_mode()
1258 REG_RMW_BUFFER_FLUSH(ah); in ath9k_hw_set_operating_mode()
1261 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, in ath9k_hw_get_delta_slope_vals() argument
1283 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) in ath9k_hw_ar9330_reset_war() argument
1288 npend = ath9k_hw_numtxpending(ah, i); in ath9k_hw_ar9330_reset_war()
1293 if (ah->external_reset && in ath9k_hw_ar9330_reset_war()
1297 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_ar9330_reset_war()
1300 reset_err = ah->external_reset(); in ath9k_hw_ar9330_reset_war()
1302 ath_err(ath9k_hw_common(ah), in ath9k_hw_ar9330_reset_war()
1308 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_ar9330_reset_war()
1314 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) in ath9k_hw_set_reset() argument
1319 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1320 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, in ath9k_hw_set_reset()
1322 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); in ath9k_hw_set_reset()
1325 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset()
1327 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset()
1328 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset()
1332 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset()
1335 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1339 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); in ath9k_hw_set_reset()
1340 if (AR_SREV_9340(ah)) in ath9k_hw_set_reset()
1348 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_set_reset()
1351 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1353 REG_WRITE(ah, AR_RC, val); in ath9k_hw_set_reset()
1355 } else if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1356 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset()
1363 if (AR_SREV_9330(ah)) { in ath9k_hw_set_reset()
1364 if (!ath9k_hw_ar9330_reset_war(ah, type)) in ath9k_hw_set_reset()
1368 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_reset()
1369 ar9003_mci_check_gpm_offset(ah); in ath9k_hw_set_reset()
1371 REG_WRITE(ah, AR_RTC_RC, rst_flags); in ath9k_hw_set_reset()
1373 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset()
1375 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1377 else if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1382 REG_WRITE(ah, AR_RTC_RC, 0); in ath9k_hw_set_reset()
1383 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_reset()
1384 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); in ath9k_hw_set_reset()
1388 if (!AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1389 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1391 if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1397 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) in ath9k_hw_set_reset_power_on() argument
1399 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset_power_on()
1401 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_power_on()
1402 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_power_on()
1406 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset_power_on()
1409 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1410 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset_power_on()
1412 REG_WRITE(ah, AR_RTC_RESET, 0); in ath9k_hw_set_reset_power_on()
1414 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset_power_on()
1418 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1419 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1421 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_set_reset_power_on()
1423 if (!ath9k_hw_wait(ah, in ath9k_hw_set_reset_power_on()
1428 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); in ath9k_hw_set_reset_power_on()
1432 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); in ath9k_hw_set_reset_power_on()
1435 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) in ath9k_hw_set_reset_reg() argument
1439 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_reg()
1440 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_reg()
1444 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_reset_reg()
1447 if (!ah->reset_power_on) in ath9k_hw_set_reset_reg()
1452 ret = ath9k_hw_set_reset_power_on(ah); in ath9k_hw_set_reset_reg()
1454 ah->reset_power_on = true; in ath9k_hw_set_reset_reg()
1458 ret = ath9k_hw_set_reset(ah, type); in ath9k_hw_set_reset_reg()
1467 static bool ath9k_hw_chip_reset(struct ath_hw *ah, in ath9k_hw_chip_reset() argument
1472 if (AR_SREV_9280(ah)) { in ath9k_hw_chip_reset()
1473 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) in ath9k_hw_chip_reset()
1477 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || in ath9k_hw_chip_reset()
1478 (REG_READ(ah, AR_CR) & AR_CR_RXE)) in ath9k_hw_chip_reset()
1481 if (!ath9k_hw_set_reset_reg(ah, reset_type)) in ath9k_hw_chip_reset()
1484 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_chip_reset()
1487 ah->chip_fullsleep = false; in ath9k_hw_chip_reset()
1489 if (AR_SREV_9330(ah)) in ath9k_hw_chip_reset()
1490 ar9003_hw_internal_regulator_apply(ah); in ath9k_hw_chip_reset()
1491 ath9k_hw_init_pll(ah, chan); in ath9k_hw_chip_reset()
1496 static bool ath9k_hw_channel_change(struct ath_hw *ah, in ath9k_hw_channel_change() argument
1499 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_channel_change()
1500 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_channel_change()
1507 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; in ath9k_hw_channel_change()
1513 if (ath9k_hw_numtxpending(ah, qnum)) { in ath9k_hw_channel_change()
1520 if (!ath9k_hw_rfbus_req(ah)) { in ath9k_hw_channel_change()
1526 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_channel_change()
1530 ath9k_hw_init_pll(ah, chan); in ath9k_hw_channel_change()
1532 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { in ath9k_hw_channel_change()
1538 ath9k_hw_set_channel_regs(ah, chan); in ath9k_hw_channel_change()
1540 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_channel_change()
1545 ath9k_hw_set_clockrate(ah); in ath9k_hw_channel_change()
1546 ath9k_hw_apply_txpower(ah, chan, false); in ath9k_hw_channel_change()
1548 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_channel_change()
1549 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_channel_change()
1552 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_channel_change()
1554 ath9k_hw_init_bb(ah, chan); in ath9k_hw_channel_change()
1555 ath9k_hw_rfbus_done(ah); in ath9k_hw_channel_change()
1558 ah->ah_flags |= AH_FASTCC; in ath9k_hw_channel_change()
1559 ath9k_hw_init_cal(ah, chan); in ath9k_hw_channel_change()
1560 ah->ah_flags &= ~AH_FASTCC; in ath9k_hw_channel_change()
1566 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) in ath9k_hw_apply_gpio_override() argument
1568 u32 gpio_mask = ah->gpio_mask; in ath9k_hw_apply_gpio_override()
1575 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); in ath9k_hw_apply_gpio_override()
1576 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); in ath9k_hw_apply_gpio_override()
1580 void ath9k_hw_check_nav(struct ath_hw *ah) in ath9k_hw_check_nav() argument
1582 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_check_nav()
1585 val = REG_READ(ah, AR_NAV); in ath9k_hw_check_nav()
1588 REG_WRITE(ah, AR_NAV, 0); in ath9k_hw_check_nav()
1593 bool ath9k_hw_check_alive(struct ath_hw *ah) in ath9k_hw_check_alive() argument
1598 if (AR_SREV_9300(ah)) in ath9k_hw_check_alive()
1599 return !ath9k_hw_detect_mac_hang(ah); in ath9k_hw_check_alive()
1601 if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_check_alive()
1604 last_val = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1606 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1629 static void ath9k_hw_init_mfp(struct ath_hw *ah) in ath9k_hw_init_mfp() argument
1632 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1635 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, in ath9k_hw_init_mfp()
1637 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) in ath9k_hw_init_mfp()
1638 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1640 ah->sw_mgmt_crypto_tx = false; in ath9k_hw_init_mfp()
1641 ah->sw_mgmt_crypto_rx = false; in ath9k_hw_init_mfp()
1642 } else if (AR_SREV_9160_10_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1644 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1646 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1648 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1649 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1651 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1652 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1656 static void ath9k_hw_reset_opmode(struct ath_hw *ah, in ath9k_hw_reset_opmode() argument
1659 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset_opmode()
1661 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset_opmode()
1663 REG_RMW(ah, AR_STA_ID1, macStaId1 in ath9k_hw_reset_opmode()
1665 | ah->sta_id1_defaults, in ath9k_hw_reset_opmode()
1668 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ath9k_hw_reset_opmode()
1669 ath9k_hw_write_associd(ah); in ath9k_hw_reset_opmode()
1670 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset_opmode()
1671 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_reset_opmode()
1673 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset_opmode()
1675 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_reset_opmode()
1678 static void ath9k_hw_init_queues(struct ath_hw *ah) in ath9k_hw_init_queues() argument
1682 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_queues()
1685 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ath9k_hw_init_queues()
1687 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_queues()
1689 ah->intr_txqs = 0; in ath9k_hw_init_queues()
1691 ath9k_hw_resettxqueue(ah, i); in ath9k_hw_init_queues()
1697 static void ath9k_hw_init_desc(struct ath_hw *ah) in ath9k_hw_init_desc() argument
1699 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_desc()
1701 if (AR_SREV_9100(ah)) { in ath9k_hw_init_desc()
1703 mask = REG_READ(ah, AR_CFG); in ath9k_hw_init_desc()
1709 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_init_desc()
1711 REG_READ(ah, AR_CFG)); in ath9k_hw_init_desc()
1716 if (AR_SREV_9271(ah)) in ath9k_hw_init_desc()
1717 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in ath9k_hw_init_desc()
1719 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1722 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || in ath9k_hw_init_desc()
1723 AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_desc()
1724 AR_SREV_9561(ah)) in ath9k_hw_init_desc()
1725 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); in ath9k_hw_init_desc()
1727 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1736 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_do_fastcc() argument
1738 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_do_fastcc()
1739 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_do_fastcc()
1742 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) in ath9k_hw_do_fastcc()
1745 if (ah->chip_fullsleep) in ath9k_hw_do_fastcc()
1748 if (!ah->curchan) in ath9k_hw_do_fastcc()
1751 if (chan->channel == ah->curchan->channel) in ath9k_hw_do_fastcc()
1754 if ((ah->curchan->channelFlags | chan->channelFlags) & in ath9k_hw_do_fastcc()
1762 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) in ath9k_hw_do_fastcc()
1765 if (!ath9k_hw_check_alive(ah)) in ath9k_hw_do_fastcc()
1772 if (AR_SREV_9462(ah) && (ah->caldata && in ath9k_hw_do_fastcc()
1773 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1774 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1775 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) in ath9k_hw_do_fastcc()
1779 ah->curchan->channel, chan->channel); in ath9k_hw_do_fastcc()
1781 ret = ath9k_hw_channel_change(ah, chan); in ath9k_hw_do_fastcc()
1785 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_do_fastcc()
1786 ar9003_mci_2g5g_switch(ah, false); in ath9k_hw_do_fastcc()
1788 ath9k_hw_loadnf(ah, ah->curchan); in ath9k_hw_do_fastcc()
1789 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_do_fastcc()
1791 if (AR_SREV_9271(ah)) in ath9k_hw_do_fastcc()
1792 ar9002_hw_load_ani_reg(ah, chan); in ath9k_hw_do_fastcc()
1816 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_reset() argument
1819 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset()
1827 bool save_fullsleep = ah->chip_fullsleep; in ath9k_hw_reset()
1829 if (ath9k_hw_mci_is_enabled(ah)) { in ath9k_hw_reset()
1830 start_mci_reset = ar9003_mci_start_reset(ah, chan); in ath9k_hw_reset()
1835 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_reset()
1838 if (ah->curchan && !ah->chip_fullsleep) in ath9k_hw_reset()
1839 ath9k_hw_getnf(ah, ah->curchan); in ath9k_hw_reset()
1841 ah->caldata = caldata; in ath9k_hw_reset()
1846 ath9k_init_nfcal_hist_buffer(ah, chan); in ath9k_hw_reset()
1850 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); in ath9k_hw_reset()
1853 r = ath9k_hw_do_fastcc(ah, chan); in ath9k_hw_reset()
1858 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1859 ar9003_mci_stop_bt(ah, save_fullsleep); in ath9k_hw_reset()
1861 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); in ath9k_hw_reset()
1865 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; in ath9k_hw_reset()
1868 tsf = ath9k_hw_gettsf64(ah); in ath9k_hw_reset()
1871 saveLedState = REG_READ(ah, AR_CFG_LED) & in ath9k_hw_reset()
1875 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_reset()
1877 ah->paprd_table_write_done = false; in ath9k_hw_reset()
1880 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1881 REG_WRITE(ah, in ath9k_hw_reset()
1887 if (!ath9k_hw_chip_reset(ah, chan)) { in ath9k_hw_reset()
1893 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1894 ah->htc_reset_init = false; in ath9k_hw_reset()
1895 REG_WRITE(ah, in ath9k_hw_reset()
1903 ath9k_hw_settsf64(ah, tsf + usec); in ath9k_hw_reset()
1905 if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_reset()
1906 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ath9k_hw_reset()
1908 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
1909 ar9002_hw_enable_async_fifo(ah); in ath9k_hw_reset()
1911 r = ath9k_hw_process_ini(ah, chan); in ath9k_hw_reset()
1915 ath9k_hw_set_rfmode(ah, chan); in ath9k_hw_reset()
1917 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1918 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); in ath9k_hw_reset()
1926 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { in ath9k_hw_reset()
1928 ath9k_hw_settsf64(ah, tsf); in ath9k_hw_reset()
1931 ath9k_hw_init_mfp(ah); in ath9k_hw_reset()
1933 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_reset()
1934 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_reset()
1935 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_reset()
1937 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); in ath9k_hw_reset()
1939 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_reset()
1943 ath9k_hw_set_clockrate(ah); in ath9k_hw_reset()
1945 ath9k_hw_init_queues(ah); in ath9k_hw_reset()
1946 ath9k_hw_init_interrupt_masks(ah, ah->opmode); in ath9k_hw_reset()
1947 ath9k_hw_ani_cache_ini_regs(ah); in ath9k_hw_reset()
1948 ath9k_hw_init_qos(ah); in ath9k_hw_reset()
1950 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_hw_reset()
1951 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); in ath9k_hw_reset()
1953 ath9k_hw_init_global_settings(ah); in ath9k_hw_reset()
1955 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_reset()
1956 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, in ath9k_hw_reset()
1958 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, in ath9k_hw_reset()
1960 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
1964 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_reset()
1966 ath9k_hw_set_dma(ah); in ath9k_hw_reset()
1968 if (!ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1969 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
1971 ENABLE_REG_RMW_BUFFER(ah); in ath9k_hw_reset()
1972 if (ah->config.rx_intr_mitigation) { in ath9k_hw_reset()
1973 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); in ath9k_hw_reset()
1974 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); in ath9k_hw_reset()
1977 if (ah->config.tx_intr_mitigation) { in ath9k_hw_reset()
1978 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); in ath9k_hw_reset()
1979 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); in ath9k_hw_reset()
1981 REG_RMW_BUFFER_FLUSH(ah); in ath9k_hw_reset()
1983 ath9k_hw_init_bb(ah, chan); in ath9k_hw_reset()
1989 if (!ath9k_hw_init_cal(ah, chan)) in ath9k_hw_reset()
1992 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) in ath9k_hw_reset()
1995 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset()
1997 ath9k_hw_restore_chainmask(ah); in ath9k_hw_reset()
1998 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); in ath9k_hw_reset()
2000 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset()
2002 ath9k_hw_gen_timer_start_tsf2(ah); in ath9k_hw_reset()
2004 ath9k_hw_init_desc(ah); in ath9k_hw_reset()
2006 if (ath9k_hw_btcoex_is_enabled(ah)) in ath9k_hw_reset()
2007 ath9k_hw_btcoex_enable(ah); in ath9k_hw_reset()
2009 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
2010 ar9003_mci_check_bt(ah); in ath9k_hw_reset()
2012 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_reset()
2013 ath9k_hw_loadnf(ah, chan); in ath9k_hw_reset()
2014 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_reset()
2017 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
2018 ar9003_hw_bb_watchdog_config(ah); in ath9k_hw_reset()
2020 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) in ath9k_hw_reset()
2021 ar9003_hw_disable_phy_restart(ah); in ath9k_hw_reset()
2023 ath9k_hw_apply_gpio_override(ah); in ath9k_hw_reset()
2025 if (AR_SREV_9565(ah) && common->bt_ant_diversity) in ath9k_hw_reset()
2026 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); in ath9k_hw_reset()
2028 if (ah->hw->conf.radar_enabled) { in ath9k_hw_reset()
2030 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); in ath9k_hw_reset()
2031 ath9k_hw_set_radar_params(ah); in ath9k_hw_reset()
2046 static void ath9k_set_power_sleep(struct ath_hw *ah) in ath9k_set_power_sleep() argument
2048 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_sleep()
2050 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_set_power_sleep()
2051 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2052 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2053 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep()
2055 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); in ath9k_set_power_sleep()
2063 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep()
2065 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_sleep()
2068 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
2069 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_set_power_sleep()
2072 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { in ath9k_set_power_sleep()
2073 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); in ath9k_set_power_sleep()
2078 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
2079 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()
2087 static void ath9k_set_power_network_sleep(struct ath_hw *ah) in ath9k_set_power_network_sleep() argument
2089 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_set_power_network_sleep()
2091 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_network_sleep()
2095 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
2108 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2109 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, in ath9k_set_power_network_sleep()
2115 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_network_sleep()
2117 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2122 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_network_sleep()
2123 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
2126 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) in ath9k_hw_set_power_awake() argument
2132 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_power_awake()
2133 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_power_awake()
2137 if ((REG_READ(ah, AR_RTC_STATUS) & in ath9k_hw_set_power_awake()
2139 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in ath9k_hw_set_power_awake()
2142 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_power_awake()
2143 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_set_power_awake()
2145 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2146 REG_SET_BIT(ah, AR_RTC_RESET, in ath9k_hw_set_power_awake()
2149 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2151 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2157 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; in ath9k_hw_set_power_awake()
2161 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2165 ath_err(ath9k_hw_common(ah), in ath9k_hw_set_power_awake()
2171 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_power_awake()
2172 ar9003_mci_set_power_awake(ah); in ath9k_hw_set_power_awake()
2174 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake()
2179 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) in ath9k_hw_setpower() argument
2181 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_setpower()
2190 if (ah->power_mode == mode) in ath9k_hw_setpower()
2194 modes[ah->power_mode], modes[mode]); in ath9k_hw_setpower()
2198 status = ath9k_hw_set_power_awake(ah); in ath9k_hw_setpower()
2201 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_setpower()
2202 ar9003_mci_set_full_sleep(ah); in ath9k_hw_setpower()
2204 ath9k_set_power_sleep(ah); in ath9k_hw_setpower()
2205 ah->chip_fullsleep = true; in ath9k_hw_setpower()
2208 ath9k_set_power_network_sleep(ah); in ath9k_hw_setpower()
2214 ah->power_mode = mode; in ath9k_hw_setpower()
2222 if (!(ah->ah_flags & AH_UNPLUGGED)) in ath9k_hw_setpower()
2233 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) in ath9k_hw_beaconinit() argument
2237 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_beaconinit()
2239 switch (ah->opmode) { in ath9k_hw_beaconinit()
2241 REG_SET_BIT(ah, AR_TXCFG, in ath9k_hw_beaconinit()
2245 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); in ath9k_hw_beaconinit()
2246 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - in ath9k_hw_beaconinit()
2247 TU_TO_USEC(ah->config.dma_beacon_response_time)); in ath9k_hw_beaconinit()
2248 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - in ath9k_hw_beaconinit()
2249 TU_TO_USEC(ah->config.sw_beacon_response_time)); in ath9k_hw_beaconinit()
2254 ath_dbg(ath9k_hw_common(ah), BEACON, in ath9k_hw_beaconinit()
2255 "%s: unsupported opmode: %d\n", __func__, ah->opmode); in ath9k_hw_beaconinit()
2260 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2261 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2262 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2264 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_beaconinit()
2266 REG_SET_BIT(ah, AR_TIMER_MODE, flags); in ath9k_hw_beaconinit()
2270 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, in ath9k_hw_set_sta_beacon_timers() argument
2274 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_set_sta_beacon_timers()
2275 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_sta_beacon_timers()
2277 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2279 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); in ath9k_hw_set_sta_beacon_timers()
2280 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2281 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2283 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2285 REG_RMW_FIELD(ah, AR_RSSI_THR, in ath9k_hw_set_sta_beacon_timers()
2307 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2309 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2310 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2312 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
2321 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
2324 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); in ath9k_hw_set_sta_beacon_timers()
2325 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); in ath9k_hw_set_sta_beacon_timers()
2327 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2329 REG_SET_BIT(ah, AR_TIMER_MODE, in ath9k_hw_set_sta_beacon_timers()
2334 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
2364 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) in ath9k_hw_dfs_tested() argument
2367 switch (ah->hw_version.macVersion) { in ath9k_hw_dfs_tested()
2378 int ath9k_hw_fill_cap_info(struct ath_hw *ah) in ath9k_hw_fill_cap_info() argument
2380 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_fill_cap_info()
2381 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_fill_cap_info()
2382 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_fill_cap_info()
2387 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_fill_cap_info()
2390 if (ah->opmode != NL80211_IFTYPE_AP && in ath9k_hw_fill_cap_info()
2391 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { in ath9k_hw_fill_cap_info()
2401 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); in ath9k_hw_fill_cap_info()
2404 if (ah->disable_5ghz) in ath9k_hw_fill_cap_info()
2411 if (ah->disable_2ghz) in ath9k_hw_fill_cap_info()
2422 if (AR_SREV_9485(ah) || in ath9k_hw_fill_cap_info()
2423 AR_SREV_9285(ah) || in ath9k_hw_fill_cap_info()
2424 AR_SREV_9330(ah) || in ath9k_hw_fill_cap_info()
2425 AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2427 else if (!AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2429 else if (!AR_SREV_9300_20_OR_LATER(ah) || in ath9k_hw_fill_cap_info()
2430 AR_SREV_9340(ah) || in ath9k_hw_fill_cap_info()
2431 AR_SREV_9462(ah) || in ath9k_hw_fill_cap_info()
2432 AR_SREV_9531(ah)) in ath9k_hw_fill_cap_info()
2437 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); in ath9k_hw_fill_cap_info()
2442 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && in ath9k_hw_fill_cap_info()
2444 !(AR_SREV_9271(ah))) in ath9k_hw_fill_cap_info()
2446 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; in ath9k_hw_fill_cap_info()
2447 else if (AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2451 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); in ath9k_hw_fill_cap_info()
2455 ah->txchainmask = pCap->tx_chainmask; in ath9k_hw_fill_cap_info()
2456 ah->rxchainmask = pCap->rx_chainmask; in ath9k_hw_fill_cap_info()
2458 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; in ath9k_hw_fill_cap_info()
2461 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2462 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; in ath9k_hw_fill_cap_info()
2466 if (ah->hw_version.devid != AR2427_DEVID_PCIE) in ath9k_hw_fill_cap_info()
2471 if (AR_SREV_9271(ah)) in ath9k_hw_fill_cap_info()
2473 else if (AR_DEVID_7010(ah)) in ath9k_hw_fill_cap_info()
2475 else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2477 else if (AR_SREV_9287_11_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2479 else if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2481 else if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2486 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2492 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); in ath9k_hw_fill_cap_info()
2493 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { in ath9k_hw_fill_cap_info()
2494 ah->rfkill_gpio = in ath9k_hw_fill_cap_info()
2495 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); in ath9k_hw_fill_cap_info()
2496 ah->rfkill_polarity = in ath9k_hw_fill_cap_info()
2497 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); in ath9k_hw_fill_cap_info()
2502 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2507 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) in ath9k_hw_fill_cap_info()
2512 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2514 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && in ath9k_hw_fill_cap_info()
2515 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2525 if (AR_SREV_9280_20(ah)) in ath9k_hw_fill_cap_info()
2529 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2532 if (AR_SREV_9561(ah)) in ath9k_hw_fill_cap_info()
2533 ah->ent_mode = 0x3BDA000; in ath9k_hw_fill_cap_info()
2534 else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2535 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); in ath9k_hw_fill_cap_info()
2537 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) in ath9k_hw_fill_cap_info()
2540 if (AR_SREV_9285(ah)) { in ath9k_hw_fill_cap_info()
2541 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { in ath9k_hw_fill_cap_info()
2543 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2551 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2552 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) in ath9k_hw_fill_cap_info()
2556 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2557 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2564 if (ath9k_hw_dfs_tested(ah)) in ath9k_hw_fill_cap_info()
2579 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2580 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) in ath9k_hw_fill_cap_info()
2583 if (AR_SREV_9462_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2587 if (AR_SREV_9300_20_OR_LATER(ah) && in ath9k_hw_fill_cap_info()
2588 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) in ath9k_hw_fill_cap_info()
2592 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2593 ah->wow.max_patterns = MAX_NUM_PATTERN; in ath9k_hw_fill_cap_info()
2595 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; in ath9k_hw_fill_cap_info()
2605 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, in ath9k_hw_gpio_cfg_output_mux() argument
2620 if (AR_SREV_9280_20_OR_LATER(ah) in ath9k_hw_gpio_cfg_output_mux()
2622 REG_RMW(ah, addr, (type << gpio_shift), in ath9k_hw_gpio_cfg_output_mux()
2625 tmp = REG_READ(ah, addr); in ath9k_hw_gpio_cfg_output_mux()
2629 REG_WRITE(ah, addr, tmp); in ath9k_hw_gpio_cfg_output_mux()
2633 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) in ath9k_hw_cfg_gpio_input() argument
2637 BUG_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_cfg_gpio_input()
2639 if (AR_DEVID_7010(ah)) { in ath9k_hw_cfg_gpio_input()
2641 REG_RMW(ah, AR7010_GPIO_OE, in ath9k_hw_cfg_gpio_input()
2648 REG_RMW(ah, in ath9k_hw_cfg_gpio_input()
2655 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) in ath9k_hw_gpio_get() argument
2658 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) in ath9k_hw_gpio_get()
2660 if (gpio >= ah->caps.num_gpio_pins) in ath9k_hw_gpio_get()
2663 if (AR_DEVID_7010(ah)) { in ath9k_hw_gpio_get()
2665 val = REG_READ(ah, AR7010_GPIO_IN); in ath9k_hw_gpio_get()
2667 } else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_gpio_get()
2668 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & in ath9k_hw_gpio_get()
2670 else if (AR_SREV_9271(ah)) in ath9k_hw_gpio_get()
2672 else if (AR_SREV_9287_11_OR_LATER(ah)) in ath9k_hw_gpio_get()
2674 else if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_gpio_get()
2676 else if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_gpio_get()
2683 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, in ath9k_hw_cfg_output() argument
2688 if (AR_DEVID_7010(ah)) { in ath9k_hw_cfg_output()
2690 REG_RMW(ah, AR7010_GPIO_OE, in ath9k_hw_cfg_output()
2696 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); in ath9k_hw_cfg_output()
2698 REG_RMW(ah, in ath9k_hw_cfg_output()
2705 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) in ath9k_hw_set_gpio() argument
2707 if (AR_DEVID_7010(ah)) { in ath9k_hw_set_gpio()
2709 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), in ath9k_hw_set_gpio()
2714 if (AR_SREV_9271(ah)) in ath9k_hw_set_gpio()
2718 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), in ath9k_hw_set_gpio()
2725 void ath9k_hw_request_gpio(struct ath_hw *ah, u32 gpio, const char *label) in ath9k_hw_request_gpio() argument
2727 if (gpio >= ah->caps.num_gpio_pins) in ath9k_hw_request_gpio()
2734 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) in ath9k_hw_setantenna() argument
2736 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
2744 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) in ath9k_hw_getrxfilter() argument
2746 u32 bits = REG_READ(ah, AR_RX_FILTER); in ath9k_hw_getrxfilter()
2747 u32 phybits = REG_READ(ah, AR_PHY_ERR); in ath9k_hw_getrxfilter()
2758 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) in ath9k_hw_setrxfilter() argument
2762 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_setrxfilter()
2764 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_setrxfilter()
2767 REG_WRITE(ah, AR_RX_FILTER, bits); in ath9k_hw_setrxfilter()
2774 REG_WRITE(ah, AR_PHY_ERR, phybits); in ath9k_hw_setrxfilter()
2777 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2779 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2781 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_setrxfilter()
2785 bool ath9k_hw_phy_disable(struct ath_hw *ah) in ath9k_hw_phy_disable() argument
2787 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_phy_disable()
2788 ar9003_mci_bt_gain_ctrl(ah); in ath9k_hw_phy_disable()
2790 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) in ath9k_hw_phy_disable()
2793 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_phy_disable()
2794 ah->htc_reset_init = true; in ath9k_hw_phy_disable()
2799 bool ath9k_hw_disable(struct ath_hw *ah) in ath9k_hw_disable() argument
2801 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_disable()
2804 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) in ath9k_hw_disable()
2807 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_disable()
2812 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) in get_antenna_gain() argument
2821 return ah->eep_ops->get_eeprom(ah, gain_param); in get_antenna_gain()
2824 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_apply_txpower() argument
2827 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_apply_txpower()
2840 ant_gain = get_antenna_gain(ah, chan); in ath9k_hw_apply_txpower()
2844 ah->eep_ops->set_txpower(ah, chan, in ath9k_hw_apply_txpower()
2849 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) in ath9k_hw_set_txpowerlimit() argument
2851 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_set_txpowerlimit()
2852 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_txpowerlimit()
2859 ath9k_hw_apply_txpower(ah, chan, test); in ath9k_hw_set_txpowerlimit()
2866 void ath9k_hw_setopmode(struct ath_hw *ah) in ath9k_hw_setopmode() argument
2868 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_setopmode()
2872 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) in ath9k_hw_setmcastfilter() argument
2874 REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ath9k_hw_setmcastfilter()
2875 REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ath9k_hw_setmcastfilter()
2879 void ath9k_hw_write_associd(struct ath_hw *ah) in ath9k_hw_write_associd() argument
2881 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_write_associd()
2883 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); in ath9k_hw_write_associd()
2884 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | in ath9k_hw_write_associd()
2891 u64 ath9k_hw_gettsf64(struct ath_hw *ah) in ath9k_hw_gettsf64() argument
2896 tsf_upper1 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
2898 tsf_lower = REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf64()
2899 tsf_upper2 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
2911 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) in ath9k_hw_settsf64() argument
2913 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ath9k_hw_settsf64()
2914 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ath9k_hw_settsf64()
2918 void ath9k_hw_reset_tsf(struct ath_hw *ah) in ath9k_hw_reset_tsf() argument
2920 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, in ath9k_hw_reset_tsf()
2922 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_reset_tsf()
2925 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); in ath9k_hw_reset_tsf()
2929 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) in ath9k_hw_set_tsfadjust() argument
2932 ah->misc_mode |= AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
2934 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
2938 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_set11nmac2040() argument
2942 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) in ath9k_hw_set11nmac2040()
2947 REG_WRITE(ah, AR_2040_MODE, macmode); in ath9k_hw_set11nmac2040()
2981 u32 ath9k_hw_gettsf32(struct ath_hw *ah) in ath9k_hw_gettsf32() argument
2983 return REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf32()
2987 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) in ath9k_hw_gen_timer_start_tsf2() argument
2989 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start_tsf2()
2992 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); in ath9k_hw_gen_timer_start_tsf2()
2993 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); in ath9k_hw_gen_timer_start_tsf2()
2997 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, in ath_gen_timer_alloc() argument
3003 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_alloc()
3011 !AR_SREV_9300_20_OR_LATER(ah)) in ath_gen_timer_alloc()
3027 ath9k_hw_gen_timer_start_tsf2(ah); in ath_gen_timer_alloc()
3034 void ath9k_hw_gen_timer_start(struct ath_hw *ah, in ath9k_hw_gen_timer_start() argument
3039 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start()
3047 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, in ath9k_hw_gen_timer_start()
3049 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, in ath9k_hw_gen_timer_start()
3051 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_start()
3054 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_start()
3061 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3064 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3075 REG_SET_BIT(ah, AR_IMR_S5, mask); in ath9k_hw_gen_timer_start()
3077 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { in ath9k_hw_gen_timer_start()
3078 ah->imask |= ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_start()
3079 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_start()
3084 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) in ath9k_hw_gen_timer_stop() argument
3086 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_stop()
3089 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_stop()
3092 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_stop()
3097 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_stop()
3103 REG_CLR_BIT(ah, AR_IMR_S5, in ath9k_hw_gen_timer_stop()
3110 ah->imask &= ~ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_stop()
3111 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_stop()
3116 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) in ath_gen_timer_free() argument
3118 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_free()
3129 void ath_gen_timer_isr(struct ath_hw *ah) in ath_gen_timer_isr() argument
3131 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_isr()
3137 trigger_mask = ah->intr_gen_timer_trigger; in ath_gen_timer_isr()
3138 thresh_mask = ah->intr_gen_timer_thresh; in ath_gen_timer_isr()
3238 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) in ath9k_hw_name() argument
3243 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_name()
3246 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3247 ah->hw_version.macRev); in ath9k_hw_name()
3252 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3253 ah->hw_version.macRev, in ath9k_hw_name()
3254 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev in ath9k_hw_name()
3256 ah->hw_version.phyRev); in ath9k_hw_name()