Lines Matching refs:REG_CLR_BIT
729 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
1250 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1644 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
2051 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2052 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2053 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep()
2063 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep()
2073 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); in ath9k_set_power_sleep()
2109 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, in ath9k_set_power_network_sleep()
2115 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_network_sleep()
2174 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake()
2779 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
3061 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3089 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_stop()
3097 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_stop()
3103 REG_CLR_BIT(ah, AR_IMR_S5, in ath9k_hw_gen_timer_stop()