129 	struct base_eep_header_4k *pBase = &eep->baseEepHeader;  in ath9k_hw_4k_dump_eeprom()  local
139 	PR_EEP("Major Version", pBase->version >> 12);  in ath9k_hw_4k_dump_eeprom()
140 	PR_EEP("Minor Version", pBase->version & 0xFFF);  in ath9k_hw_4k_dump_eeprom()
141 	PR_EEP("Checksum", pBase->checksum);  in ath9k_hw_4k_dump_eeprom()
142 	PR_EEP("Length", pBase->length);  in ath9k_hw_4k_dump_eeprom()
143 	PR_EEP("RegDomain1", pBase->regDmn[0]);  in ath9k_hw_4k_dump_eeprom()
144 	PR_EEP("RegDomain2", pBase->regDmn[1]);  in ath9k_hw_4k_dump_eeprom()
145 	PR_EEP("TX Mask", pBase->txMask);  in ath9k_hw_4k_dump_eeprom()
146 	PR_EEP("RX Mask", pBase->rxMask);  in ath9k_hw_4k_dump_eeprom()
147 	PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));  in ath9k_hw_4k_dump_eeprom()
148 	PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));  in ath9k_hw_4k_dump_eeprom()
149 	PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &  in ath9k_hw_4k_dump_eeprom()
151 	PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &  in ath9k_hw_4k_dump_eeprom()
153 	PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &  in ath9k_hw_4k_dump_eeprom()
155 	PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &  in ath9k_hw_4k_dump_eeprom()
157 	PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));  in ath9k_hw_4k_dump_eeprom()
158 	PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);  in ath9k_hw_4k_dump_eeprom()
159 	PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);  in ath9k_hw_4k_dump_eeprom()
160 	PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);  in ath9k_hw_4k_dump_eeprom()
161 	PR_EEP("TX Gain type", pBase->txGainType);  in ath9k_hw_4k_dump_eeprom()
164 			 pBase->macAddr);  in ath9k_hw_4k_dump_eeprom()
302 	struct base_eep_header_4k *pBase = &eep->baseEepHeader;  in ath9k_hw_4k_get_eeprom()  local
305 	ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;  in ath9k_hw_4k_get_eeprom()
311 		return get_unaligned_be16(pBase->macAddr);  in ath9k_hw_4k_get_eeprom()
313 		return get_unaligned_be16(pBase->macAddr + 2);  in ath9k_hw_4k_get_eeprom()
315 		return get_unaligned_be16(pBase->macAddr + 4);  in ath9k_hw_4k_get_eeprom()
317 		return pBase->regDmn[0];  in ath9k_hw_4k_get_eeprom()
319 		return pBase->deviceCap;  in ath9k_hw_4k_get_eeprom()
321 		return pBase->opCapFlags;  in ath9k_hw_4k_get_eeprom()
323 		return pBase->rfSilent;  in ath9k_hw_4k_get_eeprom()
331 		return pBase->txMask;  in ath9k_hw_4k_get_eeprom()
333 		return pBase->rxMask;  in ath9k_hw_4k_get_eeprom()
343 		return pBase->txGainType;  in ath9k_hw_4k_get_eeprom()
834 	struct base_eep_header_4k *pBase = &eep->baseEepHeader;  in ath9k_hw_4k_set_board_values()  local
1083 	if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {  in ath9k_hw_4k_set_board_values()