Lines Matching refs:u8
275 u8 opCapFlags;
276 u8 eepMisc;
278 u8 macAddr[6];
279 u8 rxMask;
280 u8 txMask;
285 u8 deviceType;
286 u8 pwdclkind;
287 u8 fastClk5g;
288 u8 divChain;
289 u8 rxGainType;
290 u8 dacHiPwrMode_5G;
291 u8 openLoopPwrCntl;
292 u8 dacLpMode;
293 u8 txGainType;
294 u8 rcChainMask;
295 u8 desiredScaleCCK;
296 u8 pwr_table_offset;
297 u8 frac_n_5g;
298 u8 futureBase_3[21];
305 u8 opCapFlags;
306 u8 eepMisc;
308 u8 macAddr[6];
309 u8 rxMask;
310 u8 txMask;
315 u8 deviceType;
316 u8 txGainType;
322 u8 spurRangeLow;
323 u8 spurRangeHigh;
329 u8 antennaGainCh[AR5416_MAX_CHAINS];
330 u8 switchSettling;
331 u8 txRxAttenCh[AR5416_MAX_CHAINS];
332 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
333 u8 adcDesiredSize;
334 u8 pgaDesiredSize;
335 u8 xlnaGainCh[AR5416_MAX_CHAINS];
336 u8 txEndToXpaOff;
337 u8 txEndToRxOn;
338 u8 txFrameToXpaOn;
339 u8 thresh62;
340 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
341 u8 xpdGain;
342 u8 xpd;
343 u8 iqCalICh[AR5416_MAX_CHAINS];
344 u8 iqCalQCh[AR5416_MAX_CHAINS];
345 u8 pdGainOverlap;
346 u8 ob;
347 u8 db;
348 u8 xpaBiasLvl;
349 u8 pwrDecreaseFor2Chain;
350 u8 pwrDecreaseFor3Chain;
351 u8 txFrameToDataStart;
352 u8 txFrameToPaOn;
353 u8 ht40PowerIncForPdadc;
354 u8 bswAtten[AR5416_MAX_CHAINS];
355 u8 bswMargin[AR5416_MAX_CHAINS];
356 u8 swSettleHt40;
357 u8 xatten2Db[AR5416_MAX_CHAINS];
358 u8 xatten2Margin[AR5416_MAX_CHAINS];
359 u8 ob_ch1;
360 u8 db_ch1;
361 u8 lna_ctl;
362 u8 miscBits;
364 u8 futureModal[6];
370 u8 pwrPdg[2][5];
371 u8 vpdPdg[2][5];
372 u8 pcdac[2][5];
373 u8 empty[2][5];
379 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
380 u8 switchSettling;
381 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
382 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
383 u8 adcDesiredSize;
384 u8 pgaDesiredSize;
385 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
386 u8 txEndToXpaOff;
387 u8 txEndToRxOn;
388 u8 txFrameToXpaOn;
389 u8 thresh62;
390 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
391 u8 xpdGain;
392 u8 xpd;
393 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
394 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
395 u8 pdGainOverlap;
397 u8 ob_1:4, ob_0:4;
398 u8 db1_1:4, db1_0:4;
400 u8 ob_0:4, ob_1:4;
401 u8 db1_0:4, db1_1:4;
403 u8 xpaBiasLvl;
404 u8 txFrameToDataStart;
405 u8 txFrameToPaOn;
406 u8 ht40PowerIncForPdadc;
407 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
408 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
409 u8 swSettleHt40;
410 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
411 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
413 u8 db2_1:4, db2_0:4;
415 u8 db2_0:4, db2_1:4;
417 u8 version;
419 u8 ob_3:4, ob_2:4;
420 u8 antdiv_ctl1:4, ob_4:4;
421 u8 db1_3:4, db1_2:4;
422 u8 antdiv_ctl2:4, db1_4:4;
423 u8 db2_2:4, db2_3:4;
424 u8 reserved:4, db2_4:4;
426 u8 ob_2:4, ob_3:4;
427 u8 ob_4:4, antdiv_ctl1:4;
428 u8 db1_2:4, db1_3:4;
429 u8 db1_4:4, antdiv_ctl2:4;
430 u8 db2_2:4, db2_3:4;
431 u8 db2_4:4, reserved:4;
433 u8 tx_diversity;
434 u8 flc_pwr_thresh;
435 u8 bb_scale_smrt_antenna;
437 u8 futureModal[1];
445 u8 opCapFlags;
446 u8 eepMisc;
448 u8 macAddr[6];
449 u8 rxMask;
450 u8 txMask;
455 u8 deviceType;
456 u8 openLoopPwrCntl;
460 u8 futureBase[29];
467 u8 switchSettling;
468 u8 txRxAttenCh[AR9287_MAX_CHAINS];
469 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
471 u8 txEndToXpaOff;
472 u8 txEndToRxOn;
473 u8 txFrameToXpaOn;
474 u8 thresh62;
476 u8 xpdGain;
477 u8 xpd;
480 u8 pdGainOverlap;
481 u8 xpaBiasLvl;
482 u8 txFrameToDataStart;
483 u8 txFrameToPaOn;
484 u8 ht40PowerIncForPdadc;
485 u8 bswAtten[AR9287_MAX_CHAINS];
486 u8 bswMargin[AR9287_MAX_CHAINS];
487 u8 swSettleHt40;
488 u8 version;
489 u8 db1;
490 u8 db2;
491 u8 ob_cck;
492 u8 ob_psk;
493 u8 ob_qam;
494 u8 ob_pal_off;
495 u8 futureModal[30];
500 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
501 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
505 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
506 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
510 u8 bChannel;
511 u8 tPow2x[4];
515 u8 bChannel;
516 u8 tPow2x[8];
520 u8 bChannel;
521 u8 ctl;
525 u8 pwrPdg[2][5];
526 u8 vpdPdg[2][5];
527 u8 pcdac[2][5];
528 u8 empty[2][5];
532 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
533 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
558 u8 custData[64];
560 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
561 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
580 u8 ctlIndex[AR5416_NUM_CTLS];
582 u8 padding;
587 u8 custData[20];
589 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
600 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
602 u8 padding;
607 u8 custData[AR9287_DATA_SZ];
609 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
620 u8 ctlIndex[AR9287_NUM_CTLS];
622 u8 padding;
638 u8 isMultidomain;
639 u8 iso[3];
646 u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf,
653 u16 cfgCtl, u8 twiceAntennaReduction,
654 u8 powerLimit, bool test);
664 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
669 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
670 u8 *pVpdList, u16 numIntercepts,
671 u8 *pRetVpdList);
687 u8 antenna_reduction);
694 u8 *bChans, u16 availPiers,
696 u16 *pPdGainBoundaries, u8 *pPDADCValues,
699 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) in ath9k_hw_fbin2freq()