3580 	u32 regval, value, gpio;  in ar9003_hw_ant_ctrl_apply()  local
3660 		regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);  in ar9003_hw_ant_ctrl_apply()
3661 		regval &= (~AR_ANT_DIV_CTRL_ALL);  in ar9003_hw_ant_ctrl_apply()
3662 		regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;  in ar9003_hw_ant_ctrl_apply()
3664 		regval &= (~AR_PHY_ANT_DIV_LNADIV);  in ar9003_hw_ant_ctrl_apply()
3665 		regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;  in ar9003_hw_ant_ctrl_apply()
3668 			regval |= AR_ANT_DIV_ENABLE;  in ar9003_hw_ant_ctrl_apply()
3672 				regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S);  in ar9003_hw_ant_ctrl_apply()
3681 				regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S);  in ar9003_hw_ant_ctrl_apply()
3682 				regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S);  in ar9003_hw_ant_ctrl_apply()
3693 		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_ant_ctrl_apply()
3696 		regval = REG_READ(ah, AR_PHY_CCK_DETECT);  in ar9003_hw_ant_ctrl_apply()
3697 		regval &= (~AR_FAST_DIV_ENABLE);  in ar9003_hw_ant_ctrl_apply()
3698 		regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;  in ar9003_hw_ant_ctrl_apply()
3702 			regval |= AR_FAST_DIV_ENABLE;  in ar9003_hw_ant_ctrl_apply()
3704 		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);  in ar9003_hw_ant_ctrl_apply()
3707 			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);  in ar9003_hw_ant_ctrl_apply()
3712 			regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |  in ar9003_hw_ant_ctrl_apply()
3717 			regval |= (ATH_ANT_DIV_COMB_LNA1 <<  in ar9003_hw_ant_ctrl_apply()
3719 			regval |= (ATH_ANT_DIV_COMB_LNA2 <<  in ar9003_hw_ant_ctrl_apply()
3721 			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_ant_ctrl_apply()