380 	u32 regval;  in ar9002_hw_antdiv_comb_conf_get()  local
382 	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);  in ar9002_hw_antdiv_comb_conf_get()
383 	antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>  in ar9002_hw_antdiv_comb_conf_get()
385 	antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>  in ar9002_hw_antdiv_comb_conf_get()
387 	antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>  in ar9002_hw_antdiv_comb_conf_get()
397 	u32 regval;  in ar9002_hw_antdiv_comb_conf_set()  local
399 	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);  in ar9002_hw_antdiv_comb_conf_set()
400 	regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |  in ar9002_hw_antdiv_comb_conf_set()
403 	regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)  in ar9002_hw_antdiv_comb_conf_set()
405 	regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)  in ar9002_hw_antdiv_comb_conf_set()
407 	regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)  in ar9002_hw_antdiv_comb_conf_set()
410 	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);  in ar9002_hw_antdiv_comb_conf_set()
419 	u32 regval;  in ar9002_hw_set_bt_ant_diversity()  local
454 	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);  in ar9002_hw_set_bt_ant_diversity()
455 	regval &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));  in ar9002_hw_set_bt_ant_diversity()
460 	regval &= (~(AR_PHY_9285_FAST_DIV_BIAS));  in ar9002_hw_set_bt_ant_diversity()
461 	regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL);  in ar9002_hw_set_bt_ant_diversity()
462 	regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);  in ar9002_hw_set_bt_ant_diversity()
463 	regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF);  in ar9002_hw_set_bt_ant_diversity()
464 	regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB);  in ar9002_hw_set_bt_ant_diversity()
465 	regval |= SM((antdiv_ctrl1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB);  in ar9002_hw_set_bt_ant_diversity()
466 	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);  in ar9002_hw_set_bt_ant_diversity()
468 	regval = REG_READ(ah, AR_PHY_CCK_DETECT);  in ar9002_hw_set_bt_ant_diversity()
469 	regval &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);  in ar9002_hw_set_bt_ant_diversity()
470 	regval |= SM((antdiv_ctrl1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);  in ar9002_hw_set_bt_ant_diversity()
471 	REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);  in ar9002_hw_set_bt_ant_diversity()