Lines Matching refs:ah
66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_set_channel() argument
73 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9002_hw_set_channel()
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
88 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_set_channel()
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, in ar9002_hw_set_channel()
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal, in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { in ar9002_hw_set_channel()
134 ath9k_hw_analog_shift_rmw(ah, AR_AN_SYNTH9, in ar9002_hw_set_channel()
152 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
154 ah->curchan = chan; in ar9002_hw_set_channel()
167 static void ar9002_hw_spur_mitigate(struct ath_hw *ah, in ar9002_hw_spur_mitigate() argument
184 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9002_hw_spur_mitigate()
188 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); in ar9002_hw_spur_mitigate()
214 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate()
218 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate()
224 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
226 ENABLE_REGWRITE_BUFFER(ah); in ar9002_hw_spur_mitigate()
232 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
239 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ar9002_hw_spur_mitigate()
269 REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ar9002_hw_spur_mitigate()
272 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); in ar9002_hw_spur_mitigate()
274 ar5008_hw_cmn_spur_mitigate(ah, chan, bin); in ar9002_hw_spur_mitigate()
276 REGWRITE_BUFFER_FLUSH(ah); in ar9002_hw_spur_mitigate()
279 static void ar9002_olc_init(struct ath_hw *ah) in ar9002_olc_init() argument
287 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, in ar9002_olc_init()
289 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0, in ar9002_olc_init()
296 ah->originalGain[i] = in ar9002_olc_init()
297 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
299 ah->PDADCdelta = 0; in ar9002_olc_init()
303 static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah, in ar9002_hw_compute_pll_control() argument
310 if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) { in ar9002_hw_compute_pll_control()
311 if (AR_SREV_9280_20(ah)) { in ar9002_hw_compute_pll_control()
330 static void ar9002_hw_do_getnf(struct ath_hw *ah, in ar9002_hw_do_getnf() argument
335 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
338 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
339 if (IS_CHAN_HT40(ah->curchan)) in ar9002_hw_do_getnf()
342 if (!(ah->rxchainmask & BIT(1))) in ar9002_hw_do_getnf()
345 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
348 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
349 if (IS_CHAN_HT40(ah->curchan)) in ar9002_hw_do_getnf()
353 static void ar9002_hw_set_nf_limits(struct ath_hw *ah) in ar9002_hw_set_nf_limits() argument
355 if (AR_SREV_9285(ah)) { in ar9002_hw_set_nf_limits()
356 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ; in ar9002_hw_set_nf_limits()
357 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ; in ar9002_hw_set_nf_limits()
358 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ; in ar9002_hw_set_nf_limits()
359 } else if (AR_SREV_9287(ah)) { in ar9002_hw_set_nf_limits()
360 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ; in ar9002_hw_set_nf_limits()
361 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ; in ar9002_hw_set_nf_limits()
362 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ; in ar9002_hw_set_nf_limits()
363 } else if (AR_SREV_9271(ah)) { in ar9002_hw_set_nf_limits()
364 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ; in ar9002_hw_set_nf_limits()
365 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ; in ar9002_hw_set_nf_limits()
366 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ; in ar9002_hw_set_nf_limits()
368 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; in ar9002_hw_set_nf_limits()
369 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; in ar9002_hw_set_nf_limits()
370 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; in ar9002_hw_set_nf_limits()
371 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; in ar9002_hw_set_nf_limits()
372 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; in ar9002_hw_set_nf_limits()
373 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; in ar9002_hw_set_nf_limits()
377 static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah, in ar9002_hw_antdiv_comb_conf_get() argument
382 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
394 static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah, in ar9002_hw_antdiv_comb_conf_set() argument
399 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
410 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); in ar9002_hw_antdiv_comb_conf_set()
415 static void ar9002_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) in ar9002_hw_set_bt_ant_diversity() argument
417 struct ath_btcoex_hw *btcoex = &ah->btcoex_hw; in ar9002_hw_set_bt_ant_diversity()
429 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ar9002_hw_set_bt_ant_diversity()
431 REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM); in ar9002_hw_set_bt_ant_diversity()
432 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); in ar9002_hw_set_bt_ant_diversity()
444 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ar9002_hw_set_bt_ant_diversity()
450 REG_WRITE(ah, AR_PHY_SWITCH_COM, 0); in ar9002_hw_set_bt_ant_diversity()
451 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); in ar9002_hw_set_bt_ant_diversity()
454 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_set_bt_ant_diversity()
466 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); in ar9002_hw_set_bt_ant_diversity()
468 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9002_hw_set_bt_ant_diversity()
471 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9002_hw_set_bt_ant_diversity()
476 static void ar9002_hw_spectral_scan_config(struct ath_hw *ah, in ar9002_hw_spectral_scan_config() argument
482 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
486 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9002_hw_spectral_scan_config()
487 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_config()
490 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
493 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
502 if (AR_SREV_9271(ah)) in ar9002_hw_spectral_scan_config()
509 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
511 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
513 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
519 static void ar9002_hw_spectral_scan_trigger(struct ath_hw *ah) in ar9002_hw_spectral_scan_trigger() argument
521 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_trigger()
523 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_trigger()
527 static void ar9002_hw_spectral_scan_wait(struct ath_hw *ah) in ar9002_hw_spectral_scan_wait() argument
529 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_spectral_scan_wait()
532 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_wait()
540 static void ar9002_hw_tx99_start(struct ath_hw *ah, u32 qnum) in ar9002_hw_tx99_start() argument
542 REG_SET_BIT(ah, 0x9864, 0x7f000); in ar9002_hw_tx99_start()
543 REG_SET_BIT(ah, 0x9924, 0x7f00fe); in ar9002_hw_tx99_start()
544 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9002_hw_tx99_start()
545 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9002_hw_tx99_start()
546 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9002_hw_tx99_start()
547 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); in ar9002_hw_tx99_start()
548 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); in ar9002_hw_tx99_start()
549 REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum); in ar9002_hw_tx99_start()
550 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); in ar9002_hw_tx99_start()
551 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); in ar9002_hw_tx99_start()
552 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar9002_hw_tx99_start()
555 static void ar9002_hw_tx99_stop(struct ath_hw *ah) in ar9002_hw_tx99_stop() argument
557 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9002_hw_tx99_stop()
560 void ar9002_hw_attach_phy_ops(struct ath_hw *ah) in ar9002_hw_attach_phy_ops() argument
562 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9002_hw_attach_phy_ops()
563 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9002_hw_attach_phy_ops()
584 ar9002_hw_set_nf_limits(ah); in ar9002_hw_attach_phy_ops()