Lines Matching refs:i
95 int i, numChains = 0; in ar9002_hw_per_calibration() local
96 for (i = 0; i < AR5416_MAX_CHAINS; i++) { in ar9002_hw_per_calibration()
97 if (rxchainmask & (1 << i)) in ar9002_hw_per_calibration()
118 int i; in ar9002_hw_iqcal_collect() local
120 for (i = 0; i < AR5416_MAX_CHAINS; i++) { in ar9002_hw_iqcal_collect()
121 ah->totalPowerMeasI[i] += in ar9002_hw_iqcal_collect()
122 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
123 ah->totalPowerMeasQ[i] += in ar9002_hw_iqcal_collect()
124 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
125 ah->totalIqCorrMeas[i] += in ar9002_hw_iqcal_collect()
126 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
129 ah->cal_samples, i, ah->totalPowerMeasI[i], in ar9002_hw_iqcal_collect()
130 ah->totalPowerMeasQ[i], in ar9002_hw_iqcal_collect()
131 ah->totalIqCorrMeas[i]); in ar9002_hw_iqcal_collect()
137 int i; in ar9002_hw_adc_gaincal_collect() local
139 for (i = 0; i < AR5416_MAX_CHAINS; i++) { in ar9002_hw_adc_gaincal_collect()
140 ah->totalAdcIOddPhase[i] += in ar9002_hw_adc_gaincal_collect()
141 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
142 ah->totalAdcIEvenPhase[i] += in ar9002_hw_adc_gaincal_collect()
143 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
144 ah->totalAdcQOddPhase[i] += in ar9002_hw_adc_gaincal_collect()
145 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
146 ah->totalAdcQEvenPhase[i] += in ar9002_hw_adc_gaincal_collect()
147 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
151 ah->cal_samples, i, in ar9002_hw_adc_gaincal_collect()
152 ah->totalAdcIOddPhase[i], in ar9002_hw_adc_gaincal_collect()
153 ah->totalAdcIEvenPhase[i], in ar9002_hw_adc_gaincal_collect()
154 ah->totalAdcQOddPhase[i], in ar9002_hw_adc_gaincal_collect()
155 ah->totalAdcQEvenPhase[i]); in ar9002_hw_adc_gaincal_collect()
161 int i; in ar9002_hw_adc_dccal_collect() local
163 for (i = 0; i < AR5416_MAX_CHAINS; i++) { in ar9002_hw_adc_dccal_collect()
164 ah->totalAdcDcOffsetIOddPhase[i] += in ar9002_hw_adc_dccal_collect()
165 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
166 ah->totalAdcDcOffsetIEvenPhase[i] += in ar9002_hw_adc_dccal_collect()
167 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
168 ah->totalAdcDcOffsetQOddPhase[i] += in ar9002_hw_adc_dccal_collect()
169 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_dccal_collect()
170 ah->totalAdcDcOffsetQEvenPhase[i] += in ar9002_hw_adc_dccal_collect()
171 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_dccal_collect()
175 ah->cal_samples, i, in ar9002_hw_adc_dccal_collect()
176 ah->totalAdcDcOffsetIOddPhase[i], in ar9002_hw_adc_dccal_collect()
177 ah->totalAdcDcOffsetIEvenPhase[i], in ar9002_hw_adc_dccal_collect()
178 ah->totalAdcDcOffsetQOddPhase[i], in ar9002_hw_adc_dccal_collect()
179 ah->totalAdcDcOffsetQEvenPhase[i]); in ar9002_hw_adc_dccal_collect()
189 int iqCorrNeg, i; in ar9002_hw_iqcalibrate() local
191 for (i = 0; i < numChains; i++) { in ar9002_hw_iqcalibrate()
192 powerMeasI = ah->totalPowerMeasI[i]; in ar9002_hw_iqcalibrate()
193 powerMeasQ = ah->totalPowerMeasQ[i]; in ar9002_hw_iqcalibrate()
194 iqCorrMeas = ah->totalIqCorrMeas[i]; in ar9002_hw_iqcalibrate()
198 i); in ar9002_hw_iqcalibrate()
202 i, ah->totalIqCorrMeas[i]); in ar9002_hw_iqcalibrate()
212 i, powerMeasI); in ar9002_hw_iqcalibrate()
214 i, powerMeasQ); in ar9002_hw_iqcalibrate()
225 i, iCoff); in ar9002_hw_iqcalibrate()
227 i, qCoff); in ar9002_hw_iqcalibrate()
231 "New: Chn %d iCoff = 0x%08x\n", i, iCoff); in ar9002_hw_iqcalibrate()
242 i, iCoff, qCoff); in ar9002_hw_iqcalibrate()
244 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
247 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
252 i); in ar9002_hw_iqcalibrate()
264 u32 qGainMismatch, iGainMismatch, val, i; in ar9002_hw_adc_gaincal_calibrate() local
266 for (i = 0; i < numChains; i++) { in ar9002_hw_adc_gaincal_calibrate()
267 iOddMeasOffset = ah->totalAdcIOddPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
268 iEvenMeasOffset = ah->totalAdcIEvenPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
269 qOddMeasOffset = ah->totalAdcQOddPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
270 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
273 "Starting ADC Gain Cal for Chain %d\n", i); in ar9002_hw_adc_gaincal_calibrate()
276 i, iOddMeasOffset); in ar9002_hw_adc_gaincal_calibrate()
278 i, iEvenMeasOffset); in ar9002_hw_adc_gaincal_calibrate()
280 i, qOddMeasOffset); in ar9002_hw_adc_gaincal_calibrate()
282 i, qEvenMeasOffset); in ar9002_hw_adc_gaincal_calibrate()
294 i, iGainMismatch); in ar9002_hw_adc_gaincal_calibrate()
297 i, qGainMismatch); in ar9002_hw_adc_gaincal_calibrate()
299 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); in ar9002_hw_adc_gaincal_calibrate()
302 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_gaincal_calibrate()
305 "ADC Gain Cal done for Chain %d\n", i); in ar9002_hw_adc_gaincal_calibrate()
317 u32 iOddMeasOffset, iEvenMeasOffset, val, i; in ar9002_hw_adc_dccal_calibrate() local
324 for (i = 0; i < numChains; i++) { in ar9002_hw_adc_dccal_calibrate()
325 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i]; in ar9002_hw_adc_dccal_calibrate()
326 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i]; in ar9002_hw_adc_dccal_calibrate()
327 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; in ar9002_hw_adc_dccal_calibrate()
328 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; in ar9002_hw_adc_dccal_calibrate()
331 "Starting ADC DC Offset Cal for Chain %d\n", i); in ar9002_hw_adc_dccal_calibrate()
334 i, iOddMeasOffset); in ar9002_hw_adc_dccal_calibrate()
336 i, iEvenMeasOffset); in ar9002_hw_adc_dccal_calibrate()
338 i, qOddMeasOffset); in ar9002_hw_adc_dccal_calibrate()
340 i, qEvenMeasOffset); in ar9002_hw_adc_dccal_calibrate()
349 i, iDcMismatch); in ar9002_hw_adc_dccal_calibrate()
352 i, qDcMismatch); in ar9002_hw_adc_dccal_calibrate()
354 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); in ar9002_hw_adc_dccal_calibrate()
357 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_dccal_calibrate()
360 "ADC DC Offset Cal done for Chain %d\n", i); in ar9002_hw_adc_dccal_calibrate()
400 u32 rddata, i; in ar9280_hw_olc_temp_compensation() local
416 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) { in ar9280_hw_olc_temp_compensation()
417 regval = ah->originalGain[i] - delta; in ar9280_hw_olc_temp_compensation()
422 AR_PHY_TX_GAIN_TBL1 + i * 4, in ar9280_hw_olc_temp_compensation()
431 unsigned int i; in ar9271_hw_pa_cal() local
490 for (i = 6; i > 0; i--) { in ar9271_hw_pa_cal()
492 regVal |= (1 << (20 + i)); in ar9271_hw_pa_cal()
496 regVal &= (~(0x1 << (20 + i))); in ar9271_hw_pa_cal()
499 << (20 + i)); in ar9271_hw_pa_cal()
526 for (i = 0; i < ARRAY_SIZE(regList); i++) in ar9271_hw_pa_cal()
527 REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9271_hw_pa_cal()
536 int i, offset, offs_6_1, offs_0; in ar9285_hw_pa_cal() local
555 for (i = 0; i < ARRAY_SIZE(regList); i++) in ar9285_hw_pa_cal()
556 regList[i][1] = REG_READ(ah, regList[i][0]); in ar9285_hw_pa_cal()
585 for (i = 6; i > 0; i--) { in ar9285_hw_pa_cal()
587 regVal |= (1 << (19 + i)); in ar9285_hw_pa_cal()
591 regVal &= (~(0x1 << (19 + i))); in ar9285_hw_pa_cal()
593 regVal |= (reg_field << (19 + i)); in ar9285_hw_pa_cal()
630 for (i = 0; i < ARRAY_SIZE(regList); i++) in ar9285_hw_pa_cal()
631 REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9285_hw_pa_cal()
759 int i; in ar9285_hw_clc() local
775 for (i = 0; i < (txgain_max+1); i++) { in ar9285_hw_clc()
776 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) & in ar9285_hw_clc()
784 for (i = 0; i < clc_num; i++) { in ar9285_hw_clc()
785 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()
787 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()