Lines Matching refs:ah
64 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) in ar5008_write_bank6() argument
66 struct ar5416IniArray *array = &ah->iniBank6; in ar5008_write_bank6()
67 u32 *data = ah->analogBank6Data; in ar5008_write_bank6()
70 ENABLE_REGWRITE_BUFFER(ah); in ar5008_write_bank6()
73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
77 REGWRITE_BUFFER_FLUSH(ah); in ar5008_write_bank6()
144 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) in ar5008_hw_force_bias() argument
146 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_force_bias()
151 if (!AR_SREV_5416(ah) || synth_freq >= 3000) in ar5008_hw_force_bias()
154 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); in ar5008_hw_force_bias()
170 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); in ar5008_hw_force_bias()
173 ar5008_write_bank6(ah, ®_writes); in ar5008_hw_force_bias()
185 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar5008_hw_set_channel() argument
187 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_set_channel()
195 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar5008_hw_set_channel()
215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar5008_hw_set_channel()
218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
232 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ar5008_hw_set_channel()
244 ar5008_hw_force_bias(ah, freq); in ar5008_hw_set_channel()
250 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
252 ah->curchan = chan; in ar5008_hw_set_channel()
257 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah, in ar5008_hw_cmn_spur_mitigate() argument
297 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_cmn_spur_mitigate()
298 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_cmn_spur_mitigate()
330 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
331 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
341 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
342 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
352 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
353 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
363 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
364 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
374 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
375 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
385 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
386 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
396 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
397 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
407 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
408 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
419 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, in ar5008_hw_spur_mitigate() argument
434 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); in ar5008_hw_spur_mitigate()
449 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
455 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
462 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5008_hw_spur_mitigate()
473 REG_WRITE(ah, AR_PHY_TIMING11, new); in ar5008_hw_spur_mitigate()
475 ar5008_hw_cmn_spur_mitigate(ah, chan, bin); in ar5008_hw_spur_mitigate()
484 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) in ar5008_hw_rf_alloc_ext_banks() argument
486 int size = ah->iniBank6.ia_rows * sizeof(u32); in ar5008_hw_rf_alloc_ext_banks()
488 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_rf_alloc_ext_banks()
491 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); in ar5008_hw_rf_alloc_ext_banks()
492 if (!ah->analogBank6Data) in ar5008_hw_rf_alloc_ext_banks()
511 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, in ar5008_hw_set_rf_regs() argument
526 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_set_rf_regs()
530 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); in ar5008_hw_set_rf_regs()
532 for (i = 0; i < ah->iniBank6.ia_rows; i++) in ar5008_hw_set_rf_regs()
533 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); in ar5008_hw_set_rf_regs()
538 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); in ar5008_hw_set_rf_regs()
539 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); in ar5008_hw_set_rf_regs()
540 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
542 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
545 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); in ar5008_hw_set_rf_regs()
546 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); in ar5008_hw_set_rf_regs()
547 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
549 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
559 ar5008_write_bank6(ah, ®Writes); in ar5008_hw_set_rf_regs()
565 static void ar5008_hw_init_bb(struct ath_hw *ah, in ar5008_hw_init_bb() argument
570 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_init_bb()
572 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar5008_hw_init_bb()
574 ath9k_hw_synth_delay(ah, chan, synthDelay); in ar5008_hw_init_bb()
577 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) in ar5008_hw_init_chain_masks() argument
581 rx_chainmask = ah->rxchainmask; in ar5008_hw_init_chain_masks()
582 tx_chainmask = ah->txchainmask; in ar5008_hw_init_chain_masks()
587 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
590 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { in ar5008_hw_init_chain_masks()
591 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
592 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
598 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_init_chain_masks()
599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
603 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_init_chain_masks()
607 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); in ar5008_hw_init_chain_masks()
609 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_init_chain_masks()
612 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
615 if (AR_SREV_9100(ah)) in ar5008_hw_init_chain_masks()
616 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
617 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5008_hw_init_chain_masks()
620 static void ar5008_hw_override_ini(struct ath_hw *ah, in ar5008_hw_override_ini() argument
630 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5008_hw_override_ini()
632 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar5008_hw_override_ini()
640 val = REG_READ(ah, AR_PCU_MISC_MODE2) & in ar5008_hw_override_ini()
643 if (!AR_SREV_9271(ah)) in ar5008_hw_override_ini()
646 if (AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_override_ini()
651 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar5008_hw_override_ini()
654 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_override_ini()
660 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); in ar5008_hw_override_ini()
666 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { in ar5008_hw_override_ini()
667 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); in ar5008_hw_override_ini()
669 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); in ar5008_hw_override_ini()
673 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, in ar5008_hw_set_channel_regs() argument
679 if (AR_SREV_9285_12_OR_LATER(ah)) in ar5008_hw_set_channel_regs()
680 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ar5008_hw_set_channel_regs()
693 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_set_channel_regs()
694 REG_WRITE(ah, AR_PHY_TURBO, phymode); in ar5008_hw_set_channel_regs()
698 ath9k_hw_set11nmac2040(ah, chan); in ar5008_hw_set_channel_regs()
700 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
701 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
703 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_set_channel_regs()
707 static int ar5008_hw_process_ini(struct ath_hw *ah, in ar5008_hw_process_ini() argument
710 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_process_ini()
726 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5008_hw_process_ini()
729 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); in ar5008_hw_process_ini()
730 if (ah->eep_ops->set_addac) in ar5008_hw_process_ini()
731 ah->eep_ops->set_addac(ah, chan); in ar5008_hw_process_ini()
733 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); in ar5008_hw_process_ini()
734 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); in ar5008_hw_process_ini()
736 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_process_ini()
738 for (i = 0; i < ah->iniModes.ia_rows; i++) { in ar5008_hw_process_ini()
739 u32 reg = INI_RA(&ah->iniModes, i, 0); in ar5008_hw_process_ini()
740 u32 val = INI_RA(&ah->iniModes, i, modesIndex); in ar5008_hw_process_ini()
742 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) in ar5008_hw_process_ini()
745 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
748 && ah->config.analog_shiftreg in ar5008_hw_process_ini()
756 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_process_ini()
758 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_process_ini()
759 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); in ar5008_hw_process_ini()
761 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || in ar5008_hw_process_ini()
762 AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_process_ini()
763 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar5008_hw_process_ini()
765 if (AR_SREV_9271_10(ah)) { in ar5008_hw_process_ini()
766 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); in ar5008_hw_process_ini()
767 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); in ar5008_hw_process_ini()
770 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_process_ini()
773 for (i = 0; i < ah->iniCommon.ia_rows; i++) { in ar5008_hw_process_ini()
774 u32 reg = INI_RA(&ah->iniCommon, i, 0); in ar5008_hw_process_ini()
775 u32 val = INI_RA(&ah->iniCommon, i, 1); in ar5008_hw_process_ini()
777 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
780 && ah->config.analog_shiftreg in ar5008_hw_process_ini()
788 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_process_ini()
790 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); in ar5008_hw_process_ini()
792 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar5008_hw_process_ini()
793 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, in ar5008_hw_process_ini()
796 ar5008_hw_override_ini(ah, chan); in ar5008_hw_process_ini()
797 ar5008_hw_set_channel_regs(ah, chan); in ar5008_hw_process_ini()
798 ar5008_hw_init_chain_masks(ah); in ar5008_hw_process_ini()
799 ath9k_olc_init(ah); in ar5008_hw_process_ini()
800 ath9k_hw_apply_txpower(ah, chan, false); in ar5008_hw_process_ini()
803 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { in ar5008_hw_process_ini()
804 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); in ar5008_hw_process_ini()
811 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) in ar5008_hw_set_rfmode() argument
823 if (!AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_set_rfmode()
827 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar5008_hw_set_rfmode()
830 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5008_hw_set_rfmode()
833 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) in ar5008_hw_mark_phy_inactive() argument
835 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar5008_hw_mark_phy_inactive()
838 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, in ar5008_hw_set_delta_slope() argument
850 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar5008_hw_set_delta_slope()
853 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar5008_hw_set_delta_slope()
856 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5008_hw_set_delta_slope()
858 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5008_hw_set_delta_slope()
863 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar5008_hw_set_delta_slope()
866 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5008_hw_set_delta_slope()
868 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5008_hw_set_delta_slope()
872 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) in ar5008_hw_rfbus_req() argument
874 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar5008_hw_rfbus_req()
875 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ar5008_hw_rfbus_req()
879 static void ar5008_hw_rfbus_done(struct ath_hw *ah) in ar5008_hw_rfbus_done() argument
881 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_rfbus_done()
883 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar5008_hw_rfbus_done()
885 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar5008_hw_rfbus_done()
888 static void ar5008_restore_chainmask(struct ath_hw *ah) in ar5008_restore_chainmask() argument
890 int rx_chainmask = ah->rxchainmask; in ar5008_restore_chainmask()
893 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
894 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
898 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, in ar9160_hw_compute_pll_control() argument
918 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, in ar5008_hw_compute_pll_control() argument
938 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, in ar5008_hw_ani_control_new() argument
942 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_ani_control_new()
943 struct ath9k_channel *chan = ah->curchan; in ar5008_hw_ani_control_new()
944 struct ar5416AniState *aniState = &ah->ani; in ar5008_hw_ani_control_new()
947 switch (cmd & ah->ani_function) { in ar5008_hw_ani_control_new()
982 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
985 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
988 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
990 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
992 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
994 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
998 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1000 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1002 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1004 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1008 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1011 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1022 ah->stats.ast_ani_ofdmon++; in ar5008_hw_ani_control_new()
1024 ah->stats.ast_ani_ofdmoff++; in ar5008_hw_ani_control_new()
1033 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, in ar5008_hw_ani_control_new()
1035 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, in ar5008_hw_ani_control_new()
1056 ah->stats.ast_ani_stepup++; in ar5008_hw_ani_control_new()
1058 ah->stats.ast_ani_stepdown++; in ar5008_hw_ani_control_new()
1067 REG_RMW_FIELD(ah, AR_PHY_TIMING5, in ar5008_hw_ani_control_new()
1070 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ar5008_hw_ani_control_new()
1091 ah->stats.ast_ani_spurup++; in ar5008_hw_ani_control_new()
1093 ah->stats.ast_ani_spurdown++; in ar5008_hw_ani_control_new()
1122 static void ar5008_hw_do_getnf(struct ath_hw *ah, in ar5008_hw_do_getnf() argument
1127 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1130 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
1133 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); in ar5008_hw_do_getnf()
1136 if (!IS_CHAN_HT40(ah->curchan)) in ar5008_hw_do_getnf()
1139 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1142 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1145 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1154 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) in ar5008_hw_ani_cache_ini_regs() argument
1156 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_ani_cache_ini_regs()
1157 struct ath9k_channel *chan = ah->curchan; in ar5008_hw_ani_cache_ini_regs()
1158 struct ar5416AniState *aniState = &ah->ani; in ar5008_hw_ani_cache_ini_regs()
1165 ah->hw_version.macVersion, in ar5008_hw_ani_cache_ini_regs()
1166 ah->hw_version.macRev, in ar5008_hw_ani_cache_ini_regs()
1167 ah->opmode, in ar5008_hw_ani_cache_ini_regs()
1170 val = REG_READ(ah, AR_PHY_SFCORR); in ar5008_hw_ani_cache_ini_regs()
1175 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar5008_hw_ani_cache_ini_regs()
1180 val = REG_READ(ah, AR_PHY_SFCORR_EXT); in ar5008_hw_ani_cache_ini_regs()
1185 iniDef->firstep = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1188 iniDef->firstepLow = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1191 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1194 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1205 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) in ar5008_hw_set_nf_limits() argument
1207 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1208 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1209 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1210 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1211 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1212 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1215 static void ar5008_hw_set_radar_params(struct ath_hw *ah, in ar5008_hw_set_radar_params() argument
1221 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar5008_hw_set_radar_params()
1232 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); in ar5008_hw_set_radar_params()
1241 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar5008_hw_set_radar_params()
1242 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar5008_hw_set_radar_params()
1244 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
1246 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
1249 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) in ar5008_hw_set_radar_conf() argument
1251 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar5008_hw_set_radar_conf()
1263 static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array) in ar5008_hw_init_txpower_cck() argument
1266 ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]); in ar5008_hw_init_txpower_cck()
1267 ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l], in ar5008_hw_init_txpower_cck()
1269 ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l], in ar5008_hw_init_txpower_cck()
1271 ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l], in ar5008_hw_init_txpower_cck()
1276 static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array, in ar5008_hw_init_txpower_ofdm() argument
1282 ah->tx_power[i] = rate_array[idx]; in ar5008_hw_init_txpower_ofdm()
1287 static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array, in ar5008_hw_init_txpower_ht() argument
1294 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta; in ar5008_hw_init_txpower_ht()
1297 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset], in ar5008_hw_init_txpower_ht()
1301 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, in ar5008_hw_init_rate_txpower() argument
1305 ar5008_hw_init_txpower_ofdm(ah, rate_array, in ar5008_hw_init_rate_txpower()
1308 ar5008_hw_init_txpower_ht(ah, rate_array, in ar5008_hw_init_rate_txpower()
1315 ar5008_hw_init_txpower_cck(ah, rate_array); in ar5008_hw_init_rate_txpower()
1316 ar5008_hw_init_txpower_ofdm(ah, rate_array, in ar5008_hw_init_rate_txpower()
1319 ar5008_hw_init_txpower_ht(ah, rate_array, in ar5008_hw_init_rate_txpower()
1328 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) in ar5008_hw_attach_phy_ops() argument
1330 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar5008_hw_attach_phy_ops()
1341 ret = ar5008_hw_rf_alloc_ext_banks(ah); in ar5008_hw_attach_phy_ops()
1364 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ar5008_hw_attach_phy_ops()
1369 ar5008_hw_set_nf_limits(ah); in ar5008_hw_attach_phy_ops()
1370 ar5008_hw_set_radar_conf(ah); in ar5008_hw_attach_phy_ops()
1371 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); in ar5008_hw_attach_phy_ops()