130 ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_start_tx_dma()  argument
134 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_start_tx_dma()
137 	if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)  in ath5k_hw_start_tx_dma()
146 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_start_tx_dma()
168 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))  in ath5k_hw_start_tx_dma()
172 		AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);  in ath5k_hw_start_tx_dma()
188 ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_stop_tx_dma()  argument
193 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_stop_tx_dma()
196 	if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)  in ath5k_hw_stop_tx_dma()
205 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_stop_tx_dma()
228 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_stop_tx_dma()
234 		AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);  in ath5k_hw_stop_tx_dma()
238 		(AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0);  in ath5k_hw_stop_tx_dma()
242 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))  in ath5k_hw_stop_tx_dma()
244 				"queue %i didn't stop !\n", queue);  in ath5k_hw_stop_tx_dma()
250 				AR5K_QUEUE_STATUS(queue)) &  in ath5k_hw_stop_tx_dma()
286 					AR5K_QUEUE_STATUS(queue)) &  in ath5k_hw_stop_tx_dma()
297 					queue);  in ath5k_hw_stop_tx_dma()
303 		AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_stop_tx_dma()
311 					queue, pending);  in ath5k_hw_stop_tx_dma()
328 ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_stop_beacon_queue()  argument
331 	ret = ath5k_hw_stop_tx_dma(ah, queue);  in ath5k_hw_stop_beacon_queue()
353 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_get_txdp()  argument
357 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_get_txdp()
364 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_get_txdp()
376 		tx_reg = AR5K_QUEUE_TXDP(queue);  in ath5k_hw_get_txdp()
396 ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)  in ath5k_hw_set_txdp()  argument
400 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_set_txdp()
407 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_set_txdp()
424 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))  in ath5k_hw_set_txdp()
427 		tx_reg = AR5K_QUEUE_TXDP(queue);  in ath5k_hw_set_txdp()