640 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)  in ath10k_pci_read32()  function
667 	return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);  in ath10k_pci_soc_read32()
677 	return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);  in ath10k_pci_reg_read32()
690 	cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_pending()
710 	(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_disable_and_clear_legacy_irq()
722 	(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_enable_legacy_irq()
831 		val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_targ_cpu_to_ce_addr()
836 		val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);  in ath10k_pci_targ_cpu_to_ce_addr()
1498 		val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_msi_fw_mask()
1520 		val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_msi_fw_unmask()
1857 	val = ath10k_pci_read32(ar, addr);  in ath10k_pci_wake_target_cpu()
2117 	return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &  in ath10k_pci_has_fw_crashed()
2125 	val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);  in ath10k_pci_fw_crashed_clear()
2156 	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +  in ath10k_pci_warm_reset_cpu()
2166 	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +  in ath10k_pci_warm_reset_ce()
2180 	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +  in ath10k_pci_warm_reset_clear_lf()
2506 	.read32			= ath10k_pci_read32,
2813 		val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);  in ath10k_pci_wait_for_target_init()