249 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
252 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)  argument
253 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)  argument
254 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)  argument
255 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)  argument
392 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
452 #define CE_COUNT ar->hw_values->ce_count
466 #define MSI_ASSIGN_CE_MAX	ar->hw_values->msi_assign_ce_max
469 #define RTC_STATE_V_ON				ar->hw_values->rtc_state_val_on
471 #define RTC_STATE_COLD_RESET_MASK		ar->regs->rtc_state_cold_reset_mask
480 #define RTC_SOC_BASE_ADDRESS			ar->regs->rtc_soc_base_address
481 #define RTC_WMAC_BASE_ADDRESS			ar->regs->rtc_wmac_base_address
485 #define SOC_CORE_BASE_ADDRESS			ar->regs->soc_core_base_address
494 #define CE_WRAPPER_BASE_ADDRESS			ar->regs->ce_wrapper_base_address
495 #define CE0_BASE_ADDRESS			ar->regs->ce0_base_address
496 #define CE1_BASE_ADDRESS			ar->regs->ce1_base_address
497 #define CE2_BASE_ADDRESS			ar->regs->ce2_base_address
498 #define CE3_BASE_ADDRESS			ar->regs->ce3_base_address
499 #define CE4_BASE_ADDRESS			ar->regs->ce4_base_address
500 #define CE5_BASE_ADDRESS			ar->regs->ce5_base_address
501 #define CE6_BASE_ADDRESS			ar->regs->ce6_base_address
502 #define CE7_BASE_ADDRESS			ar->regs->ce7_base_address
505 #define PCIE_LOCAL_BASE_ADDRESS		ar->regs->pcie_local_base_address
509 #define SOC_RESET_CONTROL_SI0_RST_MASK		ar->regs->soc_reset_control_si0_rst_mask
510 #define SOC_RESET_CONTROL_CE_RST_MASK		ar->regs->soc_reset_control_ce_rst_mask
524 #define SOC_CHIP_ID_ADDRESS			ar->regs->soc_chip_id_address
579 #define PCIE_INTR_CLR_ADDRESS			ar->regs->pcie_intr_clr_address
580 #define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address
583 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)  argument
586 #define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address
591 #define PCIE_INTR_FIRMWARE_MASK			ar->regs->pcie_intr_fw_mask
592 #define PCIE_INTR_CE_MASK_ALL			ar->regs->pcie_intr_ce_mask_all