Lines Matching refs:ce_ctrl_addr
63 u32 ce_ctrl_addr, in ath10k_ce_dest_ring_write_index_set() argument
66 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n); in ath10k_ce_dest_ring_write_index_set()
70 u32 ce_ctrl_addr) in ath10k_ce_dest_ring_write_index_get() argument
72 return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS); in ath10k_ce_dest_ring_write_index_get()
76 u32 ce_ctrl_addr, in ath10k_ce_src_ring_write_index_set() argument
79 ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n); in ath10k_ce_src_ring_write_index_set()
83 u32 ce_ctrl_addr) in ath10k_ce_src_ring_write_index_get() argument
85 return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS); in ath10k_ce_src_ring_write_index_get()
89 u32 ce_ctrl_addr) in ath10k_ce_src_ring_read_index_get() argument
91 return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS); in ath10k_ce_src_ring_read_index_get()
95 u32 ce_ctrl_addr, in ath10k_ce_src_ring_base_addr_set() argument
98 ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr); in ath10k_ce_src_ring_base_addr_set()
102 u32 ce_ctrl_addr, in ath10k_ce_src_ring_size_set() argument
105 ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n); in ath10k_ce_src_ring_size_set()
109 u32 ce_ctrl_addr, in ath10k_ce_src_ring_dmax_set() argument
113 (ce_ctrl_addr) + CE_CTRL1_ADDRESS); in ath10k_ce_src_ring_dmax_set()
115 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, in ath10k_ce_src_ring_dmax_set()
121 u32 ce_ctrl_addr, in ath10k_ce_src_ring_byte_swap_set() argument
124 u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS); in ath10k_ce_src_ring_byte_swap_set()
126 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, in ath10k_ce_src_ring_byte_swap_set()
132 u32 ce_ctrl_addr, in ath10k_ce_dest_ring_byte_swap_set() argument
135 u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS); in ath10k_ce_dest_ring_byte_swap_set()
137 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, in ath10k_ce_dest_ring_byte_swap_set()
143 u32 ce_ctrl_addr) in ath10k_ce_dest_ring_read_index_get() argument
145 return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS); in ath10k_ce_dest_ring_read_index_get()
149 u32 ce_ctrl_addr, in ath10k_ce_dest_ring_base_addr_set() argument
152 ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr); in ath10k_ce_dest_ring_base_addr_set()
156 u32 ce_ctrl_addr, in ath10k_ce_dest_ring_size_set() argument
159 ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n); in ath10k_ce_dest_ring_size_set()
163 u32 ce_ctrl_addr, in ath10k_ce_src_ring_highmark_set() argument
166 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS); in ath10k_ce_src_ring_highmark_set()
168 ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS, in ath10k_ce_src_ring_highmark_set()
174 u32 ce_ctrl_addr, in ath10k_ce_src_ring_lowmark_set() argument
177 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS); in ath10k_ce_src_ring_lowmark_set()
179 ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS, in ath10k_ce_src_ring_lowmark_set()
185 u32 ce_ctrl_addr, in ath10k_ce_dest_ring_highmark_set() argument
188 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS); in ath10k_ce_dest_ring_highmark_set()
190 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS, in ath10k_ce_dest_ring_highmark_set()
196 u32 ce_ctrl_addr, in ath10k_ce_dest_ring_lowmark_set() argument
199 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS); in ath10k_ce_dest_ring_lowmark_set()
201 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS, in ath10k_ce_dest_ring_lowmark_set()
207 u32 ce_ctrl_addr) in ath10k_ce_copy_complete_inter_enable() argument
210 ce_ctrl_addr + HOST_IE_ADDRESS); in ath10k_ce_copy_complete_inter_enable()
212 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, in ath10k_ce_copy_complete_inter_enable()
217 u32 ce_ctrl_addr) in ath10k_ce_copy_complete_intr_disable() argument
220 ce_ctrl_addr + HOST_IE_ADDRESS); in ath10k_ce_copy_complete_intr_disable()
222 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, in ath10k_ce_copy_complete_intr_disable()
227 u32 ce_ctrl_addr) in ath10k_ce_watermark_intr_disable() argument
230 ce_ctrl_addr + HOST_IE_ADDRESS); in ath10k_ce_watermark_intr_disable()
232 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, in ath10k_ce_watermark_intr_disable()
237 u32 ce_ctrl_addr) in ath10k_ce_error_intr_enable() argument
240 ce_ctrl_addr + MISC_IE_ADDRESS); in ath10k_ce_error_intr_enable()
242 ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS, in ath10k_ce_error_intr_enable()
247 u32 ce_ctrl_addr) in ath10k_ce_error_intr_disable() argument
250 ce_ctrl_addr + MISC_IE_ADDRESS); in ath10k_ce_error_intr_disable()
252 ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS, in ath10k_ce_error_intr_disable()
257 u32 ce_ctrl_addr, in ath10k_ce_engine_int_status_clear() argument
260 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask); in ath10k_ce_engine_int_status_clear()