Lines Matching refs:movew

160 	movew (\src)+, (\dest)+
223 	movew #(TIMER_IRQ_LEVEL << 8) + TIMER_IRQ, PICR	// interrupt from PIT
224 	movew #PITR_CONST, PITR
243 	movew #0xFFFF, PAPAR		// all pins are clocks/data
257 	movew #0x2700, %sr		// disable IRQs again
355 	movew %d1, SCC_TBASE(%a1)	// D1 = offset of first TxBD
357 	movew %d1, SCC_RBASE(%a1)	// D1 = offset of first RxBD
367 	movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
368 	movew #2, parity_bytes(%d0)
374 	movew #0x0800, SCC_PSMR(%a2)	// CRC32-CCITT
377 	movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
378 	movew #4, parity_bytes(%d0)
387 	movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
388 	movew #2, parity_bytes(%d0)
394 	movew #0x0800, SCC_PSMR(%a2)	// CRC32-CCITT preset 0
397 	movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
398 	movew #4, parity_bytes(%d0)
405 	movew #HDLC_MAX_MRU, SCC_MFLR(%a1) // 0 bytes for CRC
418 	movew #BUFFER_LENGTH, SCC_MRBLR(%a1)
422 	movew %d1, CR			// Init SCC RX and TX params
426 	movew #0x001F, SCC_SCCM(%a2)	// TXE RXF BSY TXB RXB interrupts
468 	movew %d2, 2(%d1)		// length into BD
492 	movew (%d1), %d2		// D2 = RX BD flags
507 	movew 2(%d1), %d3
572 	movew (%d1), %d3		// D3 = TX BD flags
609 	movew %sr, -(%sp)
615 	movew #0x2700, %sr		// disable interrupts again
620 	movew %sr, -(%sp)
626 	movew #0x2700, %sr		// disable interrupts again
630 	movew (%sp)+, %sr
697 	movew (%a0), %d1		// D1 = CSR input bits
701 	movew #0x0E08, %d1
707 	movew #0x0408, %d1
713 	movew #0x0208, %d1
719 	movew #0x0D08, %d1
723 	movew #0x0008, %d1		// D1 = disable everything
724 	movew #0x80E7, %d2		// D2 = input mask: ignore DSR
728 	movew csr_output(%d0), %d2
731 	movew #0x80FF, %d2		// D2 = input mask: include DSR
736 	movew %d1, old_csr_output(%d0)
737 	movew %d1, (%a0)		// Write CSR output bits
740 	movew (PCDAT), %d1
743 	movew (%a0), %d1		// D1 = CSR input bits
748 	movew (%a0), %d1		// D1 = CSR input bits