Lines Matching refs:a0
293 movel ch_status_addr(%d0), %a0 // A0 = port status address
294 tstl STATUS_OPEN(%a0)
296 movel #1, STATUS_OPEN(%a0) // confirm the port is open
305 cmpl #CLOCK_TXFROMRX, STATUS_CLOCKING(%a0)
323 cmpl #PARITY_NONE, STATUS_PARITY(%a0)
362 cmpl #PARITY_CRC16_PR1_CCITT, STATUS_PARITY(%a0)
372 cmpl #PARITY_CRC32_PR1_CCITT, STATUS_PARITY(%a0)
382 cmpl #PARITY_CRC16_PR0_CCITT, STATUS_PARITY(%a0)
392 cmpl #PARITY_CRC32_PR0_CCITT, STATUS_PARITY(%a0)
410 cmpl #ENCODING_NRZI, STATUS_ENCODING(%a0)
435 movel scc_reg_addr(%d0), %a0 // A0 = SCC_REGS address
436 clrw SCC_SCCM(%a0) // no SCC interrupts
437 andl #0xFFFFFFCF, SCC_GSMR_L(%a0) // Disable ENT and ENR
462 movel 4(%d2), %a0 // PCI address
469 memcpy_from_pci %a0, %a1, %d2
520 movel 4(%d1), %a0 // A0 = source address
524 memcpy_to_pci %a0, %a1, %d3
690 movel %a0, -(%sp)
694 movel #CSRA, %a0 // A0 = CSR address
697 movew (%a0), %d1 // D1 = CSR input bits
737 movew %d1, (%a0) // Write CSR output bits
743 movew (%a0), %d1 // D1 = CSR input bits
748 movew (%a0), %d1 // D1 = CSR input bits
759 addl #2, %a0 // next CSR register
765 movel (%sp)+, %a0
788 movel %d0, %a0
789 addl #128 * 1024 - 4, %a0
790 cmpl (%a0), %d1
799 cmpl (%a0), %d1
803 movel %d0, %a0 // A0 = fill ptr
808 movel %a0, -(%a0)
815 cmpl (%a0)+, %a0
824 subl #4, %a0
826 movel %a0, PLX_MAILBOX_5