Lines Matching refs:u32
103 #define LMC_TDES_FIRST_BUFFER_SIZE ((u32)(0x000007FF))
104 #define LMC_TDES_SECOND_BUFFER_SIZE ((u32)(0x003FF800))
105 #define LMC_TDES_HASH_FILTERING ((u32)(0x00400000))
106 #define LMC_TDES_DISABLE_PADDING ((u32)(0x00800000))
107 #define LMC_TDES_SECOND_ADDR_CHAINED ((u32)(0x01000000))
108 #define LMC_TDES_END_OF_RING ((u32)(0x02000000))
109 #define LMC_TDES_ADD_CRC_DISABLE ((u32)(0x04000000))
110 #define LMC_TDES_SETUP_PACKET ((u32)(0x08000000))
111 #define LMC_TDES_INVERSE_FILTERING ((u32)(0x10000000))
112 #define LMC_TDES_FIRST_SEGMENT ((u32)(0x20000000))
113 #define LMC_TDES_LAST_SEGMENT ((u32)(0x40000000))
114 #define LMC_TDES_INTERRUPT_ON_COMPLETION ((u32)(0x80000000))
121 #define LMC_RDES_OVERFLOW ((u32)(0x00000001))
122 #define LMC_RDES_CRC_ERROR ((u32)(0x00000002))
123 #define LMC_RDES_DRIBBLING_BIT ((u32)(0x00000004))
124 #define LMC_RDES_REPORT_ON_MII_ERR ((u32)(0x00000008))
125 #define LMC_RDES_RCV_WATCHDOG_TIMEOUT ((u32)(0x00000010))
126 #define LMC_RDES_FRAME_TYPE ((u32)(0x00000020))
127 #define LMC_RDES_COLLISION_SEEN ((u32)(0x00000040))
128 #define LMC_RDES_FRAME_TOO_LONG ((u32)(0x00000080))
129 #define LMC_RDES_LAST_DESCRIPTOR ((u32)(0x00000100))
130 #define LMC_RDES_FIRST_DESCRIPTOR ((u32)(0x00000200))
131 #define LMC_RDES_MULTICAST_FRAME ((u32)(0x00000400))
132 #define LMC_RDES_RUNT_FRAME ((u32)(0x00000800))
133 #define LMC_RDES_DATA_TYPE ((u32)(0x00003000))
134 #define LMC_RDES_LENGTH_ERROR ((u32)(0x00004000))
135 #define LMC_RDES_ERROR_SUMMARY ((u32)(0x00008000))
136 #define LMC_RDES_FRAME_LENGTH ((u32)(0x3FFF0000))
137 #define LMC_RDES_OWN_BIT ((u32)(0x80000000))
141 #define LMC_RDES_ERROR_MASK ( (u32)( \
153 u32 n;
154 u32 m;
155 u32 v;
156 u32 x;
157 u32 r;
158 u32 f;
159 u32 exact;
166 u32 cardtype;
167 u32 clock_source; /* HSSI, T1 */
168 u32 clock_rate; /* T1 */
169 u32 crc_length;
170 u32 cable_length; /* DS3 */
171 u32 scrambler_onoff; /* DS3 */
172 u32 cable_type; /* T1 */
173 u32 keepalive_onoff; /* protocol */
174 u32 ticks; /* ticks/sec */
178 u32 circuit_type; /* T1 or E1 */
199 u32 buffer1;
200 u32 buffer2;
227 u32 version_size;
228 u32 lmc_cardtype;
230 u32 tx_ProcTimeout;
231 u32 tx_IntTimeout;
232 u32 tx_NoCompleteCnt;
233 u32 tx_MaxXmtsB4Int;
234 u32 tx_TimeoutCnt;
235 u32 tx_OutOfSyncPtr;
236 u32 tx_tbusy0;
237 u32 tx_tbusy1;
238 u32 tx_tbusy_calls;
239 u32 resetCount;
240 u32 lmc_txfull;
241 u32 tbusy;
242 u32 dirtyTx;
243 u32 lmc_next_tx;
244 u32 otherTypeCnt;
245 u32 lastType;
246 u32 lastTypeOK;
247 u32 txLoopCnt;
248 u32 usedXmtDescripCnt;
249 u32 txIndexCnt;
250 u32 rxIntLoopCnt;
252 u32 rx_SmallPktCnt;
253 u32 rx_BadPktSurgeCnt;
254 u32 rx_BuffAllocErr;
255 u32 tx_lossOfClockCnt;
258 u32 framingBitErrorCount;
259 u32 lineCodeViolationCount;
261 u32 lossOfFrameCount;
262 u32 changeOfFrameAlignmentCount;
263 u32 severelyErroredFrameCount;
265 u32 check;
269 u32 Magic0; /* BEEFCAFE */
271 u32 PciCardType;
272 u32 PciSlotNumber; /* PCI slot number */
285 u32 mii_reg16;
287 u32 Magic1; /* DEADBEEF */
301 u32 txgo;
303 volatile u32 lmc_txtick;
304 volatile u32 lmc_rxtick;
305 u32 lmc_flags;
306 u32 lmc_intrmask; /* our copy of csr_intr */
307 u32 lmc_cmdmode; /* our copy of csr_cmdmode */
308 u32 lmc_busmode; /* our copy of csr_busmode */
309 u32 lmc_gpio_io; /* state of in/out settings */
310 u32 lmc_gpio; /* state of outputs */
326 u32 last_frameerr;
330 u32 TxDescriptControlInit;
336 u32 tx_clockState;
337 u32 lmc_crcSize;
345 u32 last_int;
346 u32 num_int;
356 u32 check;
452 #define DESC_OWNED_BY_SYSTEM ((u32)(0x00000000))
453 #define DESC_OWNED_BY_DC21X4 ((u32)(0x80000000))