176 			writeb(0, &desc->stat);  in sca_init_port()
226 	u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */  in sca_msci_intr()  local
229 	sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);  in sca_msci_intr()
231 	if (stat & ST1_UDRN) {  in sca_msci_intr()
237 	if (stat & ST1_CDCD)  in sca_msci_intr()
295 	u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */  in sca_rx_intr()  local
298 	sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,  in sca_rx_intr()
301 	if (stat & DSR_BOF)  in sca_rx_intr()
314 		stat = readb(&desc->stat);  in sca_rx_intr()
315 		if (!(stat & ST_RX_EOM))  in sca_rx_intr()
317 		else if ((stat & ST_ERROR_MASK) || port->rxpart) {  in sca_rx_intr()
319 			if (stat & ST_RX_OVERRUN)  in sca_rx_intr()
321 			else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |  in sca_rx_intr()
324 			else if (stat & ST_RX_CRC)  in sca_rx_intr()
326 			if (stat & ST_RX_EOM)  in sca_rx_intr()
347 	u8 stat;  in sca_tx_intr()  local
351 	stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */  in sca_tx_intr()
354 	sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,  in sca_tx_intr()
368 		writeb(0, &desc->stat);	/* Free descriptor */  in sca_tx_intr()
381 	u8 stat;  in sca_intr()  local
385 	while((stat = sca_intr_status(card)) != 0) {  in sca_intr()
390 				if (stat & SCA_INTR_MSCI(i))  in sca_intr()
393 				if (stat & SCA_INTR_DMAC_RX(i))  in sca_intr()
396 				if (stat & SCA_INTR_DMAC_TX(i))  in sca_intr()
583 		pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));  in sca_dump_rings()
594 		pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));  in sca_dump_rings()
632 	BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */  in sca_xmit()
658 	writeb(ST_TX_EOM, &desc->stat);  in sca_xmit()
667 	if (readb(&desc->stat)) /* allow 1 packet gap */  in sca_xmit()