Lines Matching refs:u16
230 #define PHY_EDPD_CONFIG_TX_NLP_EN_ ((u16)0x8000)
231 #define PHY_EDPD_CONFIG_TX_NLP_1000_ ((u16)0x0000)
232 #define PHY_EDPD_CONFIG_TX_NLP_768_ ((u16)0x2000)
233 #define PHY_EDPD_CONFIG_TX_NLP_512_ ((u16)0x4000)
234 #define PHY_EDPD_CONFIG_TX_NLP_256_ ((u16)0x6000)
235 #define PHY_EDPD_CONFIG_RX_1_NLP_ ((u16)0x1000)
236 #define PHY_EDPD_CONFIG_RX_NLP_64_ ((u16)0x0000)
237 #define PHY_EDPD_CONFIG_RX_NLP_256_ ((u16)0x0400)
238 #define PHY_EDPD_CONFIG_RX_NLP_512_ ((u16)0x0800)
239 #define PHY_EDPD_CONFIG_RX_NLP_1000_ ((u16)0x0C00)
240 #define PHY_EDPD_CONFIG_EXT_CROSSOVER_ ((u16)0x0001)
247 #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
248 #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
251 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ ((u16)0x8000)
252 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ ((u16)0x4000)
253 #define SPECIAL_CTRL_STS_AMDIX_STATE_ ((u16)0x2000)
256 #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
257 #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
258 #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
259 #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
262 #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
263 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
264 #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
265 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
270 #define PHY_SPECIAL_SPD_ ((u16)0x001C)
271 #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
272 #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
273 #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
274 #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)