81 		phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);  in asix_get_phyid()
92 	phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);  in asix_get_phyid()
105 	return mii_link_ok(&dev->mii);  in asix_get_link()
112 	return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);  in asix_ioctl()
177 	mii_check_media(&dev->mii, 1, 1);  in ax88172_link_reset()
178 	mii_ethtool_gset(&dev->mii, &ecmd);  in ax88172_link_reset()
237 	dev->mii.dev = dev->net;  in ax88172_bind()
238 	dev->mii.mdio_read = asix_mdio_read;  in ax88172_bind()
239 	dev->mii.mdio_write = asix_mdio_write;  in ax88172_bind()
240 	dev->mii.phy_id_mask = 0x3f;  in ax88172_bind()
241 	dev->mii.reg_num_mask = 0x1f;  in ax88172_bind()
242 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88172_bind()
249 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);  in ax88172_bind()
250 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88172_bind()
252 	mii_nway_restart(&dev->mii);  in ax88172_bind()
280 	mii_check_media(&dev->mii, 1, 1);  in ax88772_link_reset()
281 	mii_ethtool_gset(&dev->mii, &ecmd);  in ax88772_link_reset()
361 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);  in ax88772_reset()
362 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88772_reset()
364 	mii_nway_restart(&dev->mii);  in ax88772_reset()
447 	dev->mii.dev = dev->net;  in ax88772_bind()
448 	dev->mii.mdio_read = asix_mdio_read;  in ax88772_bind()
449 	dev->mii.mdio_write = asix_mdio_write;  in ax88772_bind()
450 	dev->mii.phy_id_mask = 0x1f;  in ax88772_bind()
451 	dev->mii.reg_num_mask = 0x1f;  in ax88772_bind()
452 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88772_bind()
459 	embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);  in ax88772_bind()
515 	reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);  in marvell_phy_init()
518 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,  in marvell_phy_init()
522 		reg = asix_mdio_read(dev->net, dev->mii.phy_id,  in marvell_phy_init()
528 		asix_mdio_write(dev->net, dev->mii.phy_id,  in marvell_phy_init()
531 		reg = asix_mdio_read(dev->net, dev->mii.phy_id,  in marvell_phy_init()
546 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);  in rtl8211cl_phy_init()
547 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);  in rtl8211cl_phy_init()
548 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,  in rtl8211cl_phy_init()
549 		asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);  in rtl8211cl_phy_init()
550 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);  in rtl8211cl_phy_init()
553 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);  in rtl8211cl_phy_init()
554 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);  in rtl8211cl_phy_init()
555 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);  in rtl8211cl_phy_init()
563 	u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);  in marvell_led_status()
582 	asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);  in marvell_led_status()
649 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,  in ax88178_reset()
651 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88178_reset()
653 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,  in ax88178_reset()
656 	mii_nway_restart(&dev->mii);  in ax88178_reset()
685 	mii_check_media(&dev->mii, 1, 1);  in ax88178_link_reset()
686 	mii_ethtool_gset(&dev->mii, &ecmd);  in ax88178_link_reset()
802 	dev->mii.dev = dev->net;  in ax88178_bind()
803 	dev->mii.mdio_read = asix_mdio_read;  in ax88178_bind()
804 	dev->mii.mdio_write = asix_mdio_write;  in ax88178_bind()
805 	dev->mii.phy_id_mask = 0x1f;  in ax88178_bind()
806 	dev->mii.reg_num_mask = 0xff;  in ax88178_bind()
807 	dev->mii.supports_gmii = 1;  in ax88178_bind()
808 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88178_bind()