23 #define BRCM_PHY_MODEL(phydev) \  argument
24 	((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
26 #define BRCM_PHY_REV(phydev) \  argument
27 	((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
33 static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)  in bcm54xx_auxctl_write()  argument
35 	return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);  in bcm54xx_auxctl_write()
39 static int bcm50610_a0_workaround(struct phy_device *phydev)  in bcm50610_a0_workaround()  argument
43 	err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,  in bcm50610_a0_workaround()
49 	err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,  in bcm50610_a0_workaround()
54 	err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,  in bcm50610_a0_workaround()
59 	err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,  in bcm50610_a0_workaround()
64 	err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,  in bcm50610_a0_workaround()
70 static int bcm54xx_phydsp_config(struct phy_device *phydev)  in bcm54xx_phydsp_config()  argument
75 	err = bcm54xx_auxctl_write(phydev,  in bcm54xx_phydsp_config()
82 	if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||  in bcm54xx_phydsp_config()
83 	    BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {  in bcm54xx_phydsp_config()
85 		err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,  in bcm54xx_phydsp_config()
90 		if (phydev->drv->phy_id == PHY_ID_BCM50610) {  in bcm54xx_phydsp_config()
91 			err = bcm50610_a0_workaround(phydev);  in bcm54xx_phydsp_config()
97 	if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {  in bcm54xx_phydsp_config()
100 		val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);  in bcm54xx_phydsp_config()
105 		err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);  in bcm54xx_phydsp_config()
110 	err2 = bcm54xx_auxctl_write(phydev,  in bcm54xx_phydsp_config()
118 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)  in bcm54xx_adjust_rxrefclk()  argument
125 	if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&  in bcm54xx_adjust_rxrefclk()
126 	    BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&  in bcm54xx_adjust_rxrefclk()
127 	    BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)  in bcm54xx_adjust_rxrefclk()
130 	val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);  in bcm54xx_adjust_rxrefclk()
136 	if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||  in bcm54xx_adjust_rxrefclk()
137 	     BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&  in bcm54xx_adjust_rxrefclk()
138 	    BRCM_PHY_REV(phydev) >= 0x3) {  in bcm54xx_adjust_rxrefclk()
145 		if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {  in bcm54xx_adjust_rxrefclk()
152 	if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))  in bcm54xx_adjust_rxrefclk()
157 	if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)  in bcm54xx_adjust_rxrefclk()
161 		bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);  in bcm54xx_adjust_rxrefclk()
163 	val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);  in bcm54xx_adjust_rxrefclk()
169 	if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))  in bcm54xx_adjust_rxrefclk()
175 		bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);  in bcm54xx_adjust_rxrefclk()
178 static int bcm54xx_config_init(struct phy_device *phydev)  in bcm54xx_config_init()  argument
182 	reg = phy_read(phydev, MII_BCM54XX_ECR);  in bcm54xx_config_init()
188 	err = phy_write(phydev, MII_BCM54XX_ECR, reg);  in bcm54xx_config_init()
196 	err = phy_write(phydev, MII_BCM54XX_IMR, reg);  in bcm54xx_config_init()
200 	if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||  in bcm54xx_config_init()
201 	     BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&  in bcm54xx_config_init()
202 	    (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))  in bcm54xx_config_init()
203 		bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);  in bcm54xx_config_init()
205 	if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||  in bcm54xx_config_init()
206 	    (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||  in bcm54xx_config_init()
207 	    (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))  in bcm54xx_config_init()
208 		bcm54xx_adjust_rxrefclk(phydev);  in bcm54xx_config_init()
210 	bcm54xx_phydsp_config(phydev);  in bcm54xx_config_init()
215 static int bcm5482_config_init(struct phy_device *phydev)  in bcm5482_config_init()  argument
219 	err = bcm54xx_config_init(phydev);  in bcm5482_config_init()
221 	if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {  in bcm5482_config_init()
225 		reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);  in bcm5482_config_init()
226 		bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,  in bcm5482_config_init()
235 		err = bcm_phy_read_exp(phydev, reg);  in bcm5482_config_init()
238 		err = bcm_phy_write_exp(phydev, reg, err |  in bcm5482_config_init()
248 		err = bcm_phy_read_exp(phydev, reg);  in bcm5482_config_init()
251 		err = bcm_phy_write_exp(phydev, reg,  in bcm5482_config_init()
259 		reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);  in bcm5482_config_init()
260 		bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,  in bcm5482_config_init()
267 		bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,  in bcm5482_config_init()
277 		phydev->autoneg = AUTONEG_DISABLE;  in bcm5482_config_init()
278 		phydev->speed = SPEED_1000;  in bcm5482_config_init()
279 		phydev->duplex = DUPLEX_FULL;  in bcm5482_config_init()
285 static int bcm5482_read_status(struct phy_device *phydev)  in bcm5482_read_status()  argument
289 	err = genphy_read_status(phydev);  in bcm5482_read_status()
291 	if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {  in bcm5482_read_status()
296 		if (phydev->link) {  in bcm5482_read_status()
297 			phydev->speed = SPEED_1000;  in bcm5482_read_status()
298 			phydev->duplex = DUPLEX_FULL;  in bcm5482_read_status()
305 static int bcm5481_config_aneg(struct phy_device *phydev)  in bcm5481_config_aneg()  argument
310 	ret = genphy_config_aneg(phydev);  in bcm5481_config_aneg()
313 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {  in bcm5481_config_aneg()
327 		phy_write(phydev, 0x18, reg);  in bcm5481_config_aneg()
329 		reg = phy_read(phydev, 0x18);  in bcm5481_config_aneg()
334 		phy_write(phydev, 0x18, reg);  in bcm5481_config_aneg()
340 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)  in brcm_phy_setbits()  argument
344 	val = phy_read(phydev, reg);  in brcm_phy_setbits()
348 	return phy_write(phydev, reg, val | set);  in brcm_phy_setbits()
351 static int brcm_fet_config_init(struct phy_device *phydev)  in brcm_fet_config_init()  argument
356 	err = phy_write(phydev, MII_BMCR, BMCR_RESET);  in brcm_fet_config_init()
360 	reg = phy_read(phydev, MII_BRCM_FET_INTREG);  in brcm_fet_config_init()
371 	err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);  in brcm_fet_config_init()
376 	brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);  in brcm_fet_config_init()
382 	err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);  in brcm_fet_config_init()
387 	reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);  in brcm_fet_config_init()
396 	err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);  in brcm_fet_config_init()
401 	err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,  in brcm_fet_config_init()
406 	if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {  in brcm_fet_config_init()
408 		err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,  in brcm_fet_config_init()
414 	err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);  in brcm_fet_config_init()
421 static int brcm_fet_ack_interrupt(struct phy_device *phydev)  in brcm_fet_ack_interrupt()  argument
426 	reg = phy_read(phydev, MII_BRCM_FET_INTREG);  in brcm_fet_ack_interrupt()
433 static int brcm_fet_config_intr(struct phy_device *phydev)  in brcm_fet_config_intr()  argument
437 	reg = phy_read(phydev, MII_BRCM_FET_INTREG);  in brcm_fet_config_intr()
441 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)  in brcm_fet_config_intr()
446 	err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);  in brcm_fet_config_intr()