48 static void r_rc_cal_reset(struct phy_device *phydev)  in r_rc_cal_reset()  argument
51 	bcm_phy_write_exp(phydev, 0x00b0, 0x0010);  in r_rc_cal_reset()
54 	bcm_phy_write_exp(phydev, 0x00b0, 0x0000);  in r_rc_cal_reset()
57 static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)  in bcm7xxx_28nm_b0_afe_config_init()  argument
62 	bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);  in bcm7xxx_28nm_b0_afe_config_init()
65 	bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);  in bcm7xxx_28nm_b0_afe_config_init()
70 	bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);  in bcm7xxx_28nm_b0_afe_config_init()
73 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);  in bcm7xxx_28nm_b0_afe_config_init()
76 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);  in bcm7xxx_28nm_b0_afe_config_init()
78 	r_rc_cal_reset(phydev);  in bcm7xxx_28nm_b0_afe_config_init()
81 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);  in bcm7xxx_28nm_b0_afe_config_init()
84 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);  in bcm7xxx_28nm_b0_afe_config_init()
87 	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);  in bcm7xxx_28nm_b0_afe_config_init()
90 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);  in bcm7xxx_28nm_b0_afe_config_init()
93 	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);  in bcm7xxx_28nm_b0_afe_config_init()
98 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)  in bcm7xxx_28nm_d0_afe_config_init()  argument
101 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);  in bcm7xxx_28nm_d0_afe_config_init()
104 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);  in bcm7xxx_28nm_d0_afe_config_init()
107 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);  in bcm7xxx_28nm_d0_afe_config_init()
110 	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);  in bcm7xxx_28nm_d0_afe_config_init()
113 	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);  in bcm7xxx_28nm_d0_afe_config_init()
116 	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);  in bcm7xxx_28nm_d0_afe_config_init()
119 	bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);  in bcm7xxx_28nm_d0_afe_config_init()
124 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);  in bcm7xxx_28nm_d0_afe_config_init()
127 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_d0_afe_config_init()
130 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);  in bcm7xxx_28nm_d0_afe_config_init()
133 	r_rc_cal_reset(phydev);  in bcm7xxx_28nm_d0_afe_config_init()
138 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)  in bcm7xxx_28nm_e0_plus_afe_config_init()  argument
141 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);  in bcm7xxx_28nm_e0_plus_afe_config_init()
144 	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);  in bcm7xxx_28nm_e0_plus_afe_config_init()
147 	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);  in bcm7xxx_28nm_e0_plus_afe_config_init()
152 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);  in bcm7xxx_28nm_e0_plus_afe_config_init()
155 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_e0_plus_afe_config_init()
158 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);  in bcm7xxx_28nm_e0_plus_afe_config_init()
161 	r_rc_cal_reset(phydev);  in bcm7xxx_28nm_e0_plus_afe_config_init()
166 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)  in bcm7xxx_28nm_config_init()  argument
168 	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);  in bcm7xxx_28nm_config_init()
169 	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);  in bcm7xxx_28nm_config_init()
173 		     dev_name(&phydev->dev), phydev->drv->name, rev, patch);  in bcm7xxx_28nm_config_init()
180 	phy_read(phydev, MII_BMSR);  in bcm7xxx_28nm_config_init()
184 		ret = bcm7xxx_28nm_b0_afe_config_init(phydev);  in bcm7xxx_28nm_config_init()
187 		ret = bcm7xxx_28nm_d0_afe_config_init(phydev);  in bcm7xxx_28nm_config_init()
193 		ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);  in bcm7xxx_28nm_config_init()
202 	ret = bcm_phy_enable_eee(phydev);  in bcm7xxx_28nm_config_init()
206 	return bcm_phy_enable_apd(phydev, true);  in bcm7xxx_28nm_config_init()
209 static int bcm7xxx_28nm_resume(struct phy_device *phydev)  in bcm7xxx_28nm_resume()  argument
214 	ret = bcm7xxx_28nm_config_init(phydev);  in bcm7xxx_28nm_resume()
223 	return genphy_config_aneg(phydev);  in bcm7xxx_28nm_resume()
245 static int bcm7xxx_config_init(struct phy_device *phydev)  in bcm7xxx_config_init()  argument
250 	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);  in bcm7xxx_config_init()
251 	phy_read(phydev, MII_BCM7XXX_AUX_MODE);  in bcm7xxx_config_init()
254 	if (phydev->supported & PHY_GBIT_FEATURES)  in bcm7xxx_config_init()
258 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,  in bcm7xxx_config_init()
264 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);  in bcm7xxx_config_init()
268 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);  in bcm7xxx_config_init()
270 	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);  in bcm7xxx_config_init()
273 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);  in bcm7xxx_config_init()
283 static int bcm7xxx_suspend(struct phy_device *phydev)  in bcm7xxx_suspend()  argument
300 		ret = phy_write(phydev,  in bcm7xxx_suspend()
310 static int bcm7xxx_dummy_config_init(struct phy_device *phydev)  in bcm7xxx_dummy_config_init()  argument