Lines Matching refs:outb
336 outb(iobase+2, 0x00); in w83977af_probe()
340 outb(HCR_EN_IRQ, iobase+HCR); in w83977af_probe()
344 outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1); in w83977af_probe()
348 outb(HCR_SIR, iobase+HCR); in w83977af_probe()
360 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2); in w83977af_probe()
364 outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST| in w83977af_probe()
369 outb(2048 & 0xff, iobase+6); in w83977af_probe()
370 outb((2048 >> 8) & 0x1f, iobase+7); in w83977af_probe()
385 outb(0x40, iobase+7); in w83977af_probe()
415 outb(0, iobase+ICR); in w83977af_change_speed()
419 outb(0x00, iobase+ABHL); in w83977af_change_speed()
422 case 9600: outb(0x0c, iobase+ABLL); break; in w83977af_change_speed()
423 case 19200: outb(0x06, iobase+ABLL); break; in w83977af_change_speed()
424 case 38400: outb(0x03, iobase+ABLL); break; in w83977af_change_speed()
425 case 57600: outb(0x02, iobase+ABLL); break; in w83977af_change_speed()
426 case 115200: outb(0x01, iobase+ABLL); break; in w83977af_change_speed()
447 outb(ir_mode, iobase+HCR); in w83977af_change_speed()
451 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2); in w83977af_change_speed()
455 outb(0x00, iobase+UFR); /* Reset */ in w83977af_change_speed()
456 outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */ in w83977af_change_speed()
457 outb(0xa7, iobase+UFR); in w83977af_change_speed()
464 outb(ICR_EFSFI, iobase+ICR); in w83977af_change_speed()
467 outb(ICR_ERBRI, iobase+ICR); in w83977af_change_speed()
470 outb(set, iobase+SSR); in w83977af_change_speed()
526 outb(ICR_EDMAI, iobase+ICR); in w83977af_hard_xmit()
535 outb(ICR_ETXTHI, iobase+ICR); in w83977af_hard_xmit()
540 outb(set, iobase+SSR); in w83977af_hard_xmit()
561 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_write()
565 outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1); in w83977af_dma_write()
572 outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR); in w83977af_dma_write()
575 outb(set, iobase+SSR); in w83977af_dma_write()
604 outb(buf[actual++], iobase+TBR); in w83977af_pio_write()
611 outb(set, iobase+SSR); in w83977af_pio_write()
639 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_xmit_complete()
649 outb(AUDR_UNDR, iobase+AUDR); in w83977af_dma_xmit_complete()
664 outb(set, iobase+SSR); in w83977af_dma_xmit_complete()
693 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
697 outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL, in w83977af_dma_receive()
721 outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR); in w83977af_dma_receive()
728 outb(hcr | HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
732 outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
735 outb(set, iobase+SSR); in w83977af_dma_receive()
824 outb(set, iobase+SSR); in w83977af_dma_receive_complete()
856 outb(set, iobase+SSR); in w83977af_dma_receive_complete()
919 outb(AUDR_SFEND, iobase+AUDR); in w83977af_sir_interrupt()
920 outb(set, iobase+SSR); in w83977af_sir_interrupt()
979 outb(0x01, iobase+TMRL); /* 1 ms */ in w83977af_fir_interrupt()
980 outb(0x00, iobase+TMRH); in w83977af_fir_interrupt()
983 outb(IR_MSL_EN_TMR, iobase+IR_MSL); in w83977af_fir_interrupt()
992 outb(0, iobase+IR_MSL); in w83977af_fir_interrupt()
1027 outb(set, iobase+SSR); in w83977af_fir_interrupt()
1056 outb(0, iobase+ICR); /* Disable interrupts */ in w83977af_interrupt()
1066 outb(icr, iobase+ICR); /* Restore (new) interrupts */ in w83977af_interrupt()
1067 outb(set, iobase+SSR); /* Restore bank register */ in w83977af_interrupt()
1095 outb(set, iobase+SSR); in w83977af_is_receiving()
1142 outb(ICR_EFSFI, iobase+ICR); in w83977af_net_open()
1145 outb(ICR_ERBRI, iobase+ICR); in w83977af_net_open()
1148 outb(set, iobase+SSR); in w83977af_net_open()
1200 outb(0, iobase+ICR); in w83977af_net_close()
1206 outb(set, iobase+SSR); in w83977af_net_close()