Lines Matching refs:SSR
411 set = inb(iobase+SSR); in w83977af_change_speed()
470 outb(set, iobase+SSR); in w83977af_change_speed()
511 set = inb(iobase+SSR); in w83977af_hard_xmit()
540 outb(set, iobase+SSR); in w83977af_hard_xmit()
557 set = inb(iobase+SSR); in w83977af_dma_write()
575 outb(set, iobase+SSR); in w83977af_dma_write()
590 set = inb(iobase+SSR); in w83977af_pio_write()
611 outb(set, iobase+SSR); in w83977af_pio_write()
635 set = inb(iobase+SSR); in w83977af_dma_xmit_complete()
664 outb(set, iobase+SSR); in w83977af_dma_xmit_complete()
689 set = inb(iobase+SSR); in w83977af_dma_receive()
735 outb(set, iobase+SSR); in w83977af_dma_receive()
762 set = inb(iobase+SSR); in w83977af_dma_receive_complete()
824 outb(set, iobase+SSR); in w83977af_dma_receive_complete()
856 outb(set, iobase+SSR); in w83977af_dma_receive_complete()
917 set = inb(iobase+SSR); in w83977af_sir_interrupt()
920 outb(set, iobase+SSR); in w83977af_sir_interrupt()
966 set = inb(iobase+SSR); in w83977af_fir_interrupt()
1027 outb(set, iobase+SSR); in w83977af_fir_interrupt()
1050 set = inb(iobase+SSR); in w83977af_interrupt()
1067 outb(set, iobase+SSR); /* Restore bank register */ in w83977af_interrupt()
1089 set = inb(iobase+SSR); in w83977af_is_receiving()
1095 outb(set, iobase+SSR); in w83977af_is_receiving()
1137 set = inb(iobase+SSR); in w83977af_net_open()
1148 outb(set, iobase+SSR); in w83977af_net_open()
1196 set = inb(iobase+SSR); in w83977af_net_close()
1206 outb(set, iobase+SSR); in w83977af_net_close()