Lines Matching refs:iobase
281 static void SetMaxRxPacketSize(__u16 iobase, __u16 size) in SetMaxRxPacketSize() argument
287 WriteReg(iobase, I_CF_L_2, low); in SetMaxRxPacketSize()
288 WriteReg(iobase, I_CF_H_2, high); in SetMaxRxPacketSize()
296 static void SetFIFO(__u16 iobase, __u16 value) in SetFIFO() argument
300 WriteRegBit(iobase, 0x11, 0, 0); in SetFIFO()
301 WriteRegBit(iobase, 0x11, 7, 1); in SetFIFO()
304 WriteRegBit(iobase, 0x11, 0, 0); in SetFIFO()
305 WriteRegBit(iobase, 0x11, 7, 0); in SetFIFO()
308 WriteRegBit(iobase, 0x11, 0, 1); in SetFIFO()
309 WriteRegBit(iobase, 0x11, 7, 0); in SetFIFO()
312 WriteRegBit(iobase, 0x11, 0, 0); in SetFIFO()
313 WriteRegBit(iobase, 0x11, 7, 0); in SetFIFO()
407 static void SetTimer(__u16 iobase, __u8 count) in SetTimer() argument
409 EnTimerInt(iobase, OFF); in SetTimer()
410 WriteReg(iobase, TIMER, count); in SetTimer()
411 EnTimerInt(iobase, ON); in SetTimer()
415 static void SetSendByte(__u16 iobase, __u32 count) in SetSendByte() argument
422 WriteReg(iobase, TX_C_L, low); in SetSendByte()
423 WriteReg(iobase, TX_C_H, high); in SetSendByte()
427 static void ResetChip(__u16 iobase, __u8 type) in ResetChip() argument
432 WriteReg(iobase, RESET, type); in ResetChip()
435 static int CkRxRecv(__u16 iobase, struct via_ircc_cb *self) in CkRxRecv() argument
440 low = ReadReg(iobase, RX_C_L); in CkRxRecv()
441 high = ReadReg(iobase, RX_C_H); in CkRxRecv()
445 low = ReadReg(iobase, RX_C_L); in CkRxRecv()
446 high = ReadReg(iobase, RX_C_H); in CkRxRecv()
456 static __u16 RxCurCount(__u16 iobase, struct via_ircc_cb * self) in RxCurCount() argument
461 low = ReadReg(iobase, RX_P_L); in RxCurCount()
462 high = ReadReg(iobase, RX_P_H); in RxCurCount()
472 static __u16 GetRecvByte(__u16 iobase, struct via_ircc_cb * self) in GetRecvByte() argument
477 low = ReadReg(iobase, RX_P_L); in GetRecvByte()
478 high = ReadReg(iobase, RX_P_H); in GetRecvByte()
529 static void ActClk(__u16 iobase, __u8 value) in ActClk() argument
532 bTmp = ReadReg(iobase, 0x34); in ActClk()
534 WriteReg(iobase, 0x34, bTmp | Clk_bit); in ActClk()
536 WriteReg(iobase, 0x34, bTmp & ~Clk_bit); in ActClk()
539 static void ClkTx(__u16 iobase, __u8 Clk, __u8 Tx) in ClkTx() argument
543 bTmp = ReadReg(iobase, 0x34); in ClkTx()
550 WriteReg(iobase, 0x34, bTmp); in ClkTx()
558 WriteReg(iobase, 0x34, bTmp); in ClkTx()
561 static void Wr_Byte(__u16 iobase, __u8 data) in Wr_Byte() argument
567 ClkTx(iobase, 0, 1); in Wr_Byte()
570 ActClk(iobase, 1); in Wr_Byte()
576 ClkTx(iobase, 0, 1); //bit data = 1; in Wr_Byte()
578 ClkTx(iobase, 0, 0); //bit data = 1; in Wr_Byte()
582 ActClk(iobase, 1); //clk hi in Wr_Byte()
587 static __u8 Rd_Indx(__u16 iobase, __u8 addr, __u8 index) in Rd_Indx() argument
593 ClkTx(iobase, 0, 0); in Rd_Indx()
595 ActClk(iobase, 1); in Rd_Indx()
597 Wr_Byte(iobase, bTmp); in Rd_Indx()
599 ClkTx(iobase, 0, 0); in Rd_Indx()
602 ActClk(iobase, 1); in Rd_Indx()
604 ActClk(iobase, 0); in Rd_Indx()
606 ClkTx(iobase, 0, 1); in Rd_Indx()
608 bTmp = ReadReg(iobase, 0x34); in Rd_Indx()
614 ActClk(iobase, 1); in Rd_Indx()
616 ActClk(iobase, 0); in Rd_Indx()
617 bTmp = ReadReg(iobase, 0x34); in Rd_Indx()
627 ActClk(iobase, 1); in Rd_Indx()
629 ActClk(iobase, 0); in Rd_Indx()
632 bTmp = ReadReg(iobase, 0x34); in Rd_Indx()
635 ActClk(iobase, 1); in Rd_Indx()
637 ActClk(iobase, 0); in Rd_Indx()
640 ClkTx(iobase, 0, 0); in Rd_Indx()
643 ActClk(iobase, 1); in Rd_Indx()
645 ActClk(iobase, 0); in Rd_Indx()
651 static void Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data) in Wr_Indx() argument
656 ClkTx(iobase, 0, 0); in Wr_Indx()
658 ActClk(iobase, 1); in Wr_Indx()
661 Wr_Byte(iobase, bTmp); in Wr_Indx()
662 Wr_Byte(iobase, data); in Wr_Indx()
664 ClkTx(iobase, 0, 0); in Wr_Indx()
666 ActClk(iobase, 1); in Wr_Indx()
669 ActClk(iobase, 0); in Wr_Indx()
672 static void ResetDongle(__u16 iobase) in ResetDongle() argument
675 ClkTx(iobase, 0, 0); in ResetDongle()
678 ActClk(iobase, 1); in ResetDongle()
680 ActClk(iobase, 0); in ResetDongle()
683 ActClk(iobase, 0); in ResetDongle()
686 static void SetSITmode(__u16 iobase) in SetSITmode() argument
693 bTmp = ReadReg(iobase, 0x35); in SetSITmode()
694 WriteReg(iobase, 0x35, bTmp | 0x40); // Driver ITMOFF in SetSITmode()
695 WriteReg(iobase, 0x28, bTmp | 0x80); // enable All interrupt in SetSITmode()
698 static void SI_SetMode(__u16 iobase, int mode) in SI_SetMode() argument
704 SetSITmode(iobase); in SI_SetMode()
705 ResetDongle(iobase); in SI_SetMode()
707 Wr_Indx(iobase, 0x40, 0x0, 0x17); //RX ,APEN enable,Normal power in SI_SetMode()
708 Wr_Indx(iobase, 0x40, 0x1, mode); //Set Mode in SI_SetMode()
709 Wr_Indx(iobase, 0x40, 0x2, 0xff); //Set power to FIR VFIR > 1m in SI_SetMode()
710 bTmp = Rd_Indx(iobase, 0x40, 1); in SI_SetMode()
713 static void InitCard(__u16 iobase) in InitCard() argument
715 ResetChip(iobase, 5); in InitCard()
716 WriteReg(iobase, I_ST_CT_0, 0x00); // open CHIP on in InitCard()
717 SetSIRBOF(iobase, 0xc0); // hardware default value in InitCard()
718 SetSIREOF(iobase, 0xc1); in InitCard()
721 static void CommonInit(__u16 iobase) in CommonInit() argument
724 SwapDMA(iobase, OFF); in CommonInit()
725 SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095 in CommonInit()
726 EnRXFIFOReadyInt(iobase, OFF); in CommonInit()
727 EnRXFIFOHalfLevelInt(iobase, OFF); in CommonInit()
728 EnTXFIFOHalfLevelInt(iobase, OFF); in CommonInit()
729 EnTXFIFOUnderrunEOMInt(iobase, ON); in CommonInit()
731 InvertTX(iobase, OFF); in CommonInit()
732 InvertRX(iobase, OFF); in CommonInit()
734 if (IsSIROn(iobase)) { in CommonInit()
735 SIRFilter(iobase, ON); in CommonInit()
736 SIRRecvAny(iobase, ON); in CommonInit()
738 SIRFilter(iobase, OFF); in CommonInit()
739 SIRRecvAny(iobase, OFF); in CommonInit()
741 EnRXSpecInt(iobase, ON); in CommonInit()
742 WriteReg(iobase, I_ST_CT_0, 0x80); in CommonInit()
743 EnableDMA(iobase, ON); in CommonInit()
746 static void SetBaudRate(__u16 iobase, __u32 rate) in SetBaudRate() argument
750 if (IsSIROn(iobase)) { in SetBaudRate()
773 } else if (IsMIROn(iobase)) { in SetBaudRate()
775 } else if (IsFIROn(iobase)) { in SetBaudRate()
778 temp = (ReadReg(iobase, I_CF_H_1) & 0x03); in SetBaudRate()
780 WriteReg(iobase, I_CF_H_1, temp); in SetBaudRate()
783 static void SetPulseWidth(__u16 iobase, __u8 width) in SetPulseWidth() argument
787 temp = (ReadReg(iobase, I_CF_L_1) & 0x1f); in SetPulseWidth()
788 temp1 = (ReadReg(iobase, I_CF_H_1) & 0xfc); in SetPulseWidth()
793 WriteReg(iobase, I_CF_L_1, temp); in SetPulseWidth()
794 WriteReg(iobase, I_CF_H_1, temp1); in SetPulseWidth()
797 static void SetSendPreambleCount(__u16 iobase, __u8 count) in SetSendPreambleCount() argument
801 temp = ReadReg(iobase, I_CF_L_1) & 0xe0; in SetSendPreambleCount()
803 WriteReg(iobase, I_CF_L_1, temp); in SetSendPreambleCount()