458 	EnTXFIFOUnderrunEOMInt(iobase, ON);  in via_hw_init()
466 	EnRXSpecInt(iobase, ON);  in via_hw_init()
480 	SIRFilter(iobase, ON);  in via_hw_init()
481 	SetSIR(iobase, ON);  in via_hw_init()
482 	CRC16(iobase, ON);  in via_hw_init()
530 		UseOneRX(iobase, ON);	// use one RX pin   RX1,RX2  in via_ircc_change_dongle_speed()
534 		EnRX2(iobase, ON);	//sir to rx2  in via_ircc_change_dongle_speed()
539 			SlowIRRXLowActive(iobase, ON);  in via_ircc_change_dongle_speed()
558 		UseOneRX(iobase, ON);	//use ONE RX....RX1  in via_ircc_change_dongle_speed()
562 		EnRX2(iobase, ON);  in via_ircc_change_dongle_speed()
566 			SlowIRRXLowActive(iobase, ON);  in via_ircc_change_dongle_speed()
576 			SlowIRRXLowActive(iobase, ON);  in via_ircc_change_dongle_speed()
582 				WriteTX(iobase, ON);  in via_ircc_change_dongle_speed()
585 				SlowIRRXLowActive(iobase, ON);  in via_ircc_change_dongle_speed()
614 		UseOneRX(iobase, ON);	//use ONE RX....RX1  in via_ircc_change_dongle_speed()
616 		InvertRX(iobase, ON);	// invert RX pin  in via_ircc_change_dongle_speed()
618 		EnRX2(iobase, ON);	//sir to rx2  in via_ircc_change_dongle_speed()
624 			SlowIRRXLowActive(iobase, ON);  in via_ircc_change_dongle_speed()
681 		SetSIR(iobase, ON);  in via_ircc_change_speed()
682 		CRC16(iobase, ON);  in via_ircc_change_speed()
688 		SetSIR(iobase, ON);  in via_ircc_change_speed()
689 		CRC16(iobase, ON);  in via_ircc_change_speed()
693 		SetMIR(iobase, ON);  in via_ircc_change_speed()
698 		SetFIR(iobase, ON);  in via_ircc_change_speed()
702 		EnTXCRC(iobase, ON);  in via_ircc_change_speed()
706 		SetVFIR(iobase, ON);  in via_ircc_change_speed()
734 		SIRFilter(iobase, ON);  in via_ircc_change_speed()
735 		SIRRecvAny(iobase, ON);  in via_ircc_change_speed()
785 	SIRFilter(iobase, ON);  in via_ircc_hard_xmit_sir()
786 	SetSIR(iobase, ON);  in via_ircc_hard_xmit_sir()
787 	CRC16(iobase, ON);  in via_ircc_hard_xmit_sir()
804 	EnableTX(iobase, ON);  in via_ircc_hard_xmit_sir()
813 	EnAllInt(iobase, ON);  in via_ircc_hard_xmit_sir()
814 	EnTXDMA(iobase, ON);  in via_ircc_hard_xmit_sir()
822 	TXStart(iobase, ON);  in via_ircc_hard_xmit_sir()
883 	EnPhys(iobase, ON);  in via_ircc_dma_xmit()
884 	EnableTX(iobase, ON);  in via_ircc_dma_xmit()
891 	EnAllInt(iobase, ON);  in via_ircc_dma_xmit()
892 	EnTXDMA(iobase, ON);  in via_ircc_dma_xmit()
905 	TXStart(iobase, ON);  in via_ircc_dma_xmit()
996 	EnPhys(iobase, ON);  in via_ircc_dma_receive()
998 	EnableRX(iobase, ON);  in via_ircc_dma_receive()
1006 	EnAllInt(iobase, ON);  in via_ircc_dma_receive()
1008 	EnRXDMA(iobase, ON);  in via_ircc_dma_receive()
1012 	RXStart(iobase, ON);  in via_ircc_dma_receive()
1182 		RXStart(iobase, ON);  in upload_rxdata()
1400 	SIRFilter(iobase, ON);  in hwreset()
1401 	SetSIR(iobase, ON);  in hwreset()
1402 	CRC16(iobase, ON);  in hwreset()
1483 	EnAllInt(iobase, ON);  in via_ircc_net_open()