Lines Matching refs:outb
247 outb(chip->cid_index, cfg_base); in nsc_ircc_init()
563 outb(2, cfg_base); /* Mode Control Register (MCTL) */ in nsc_ircc_init_108()
564 outb(0x00, cfg_base+1); /* Disable device */ in nsc_ircc_init_108()
567 outb(CFG_108_BAIC, cfg_base); in nsc_ircc_init_108()
569 case 0x3e8: outb(0x14, cfg_base+1); break; in nsc_ircc_init_108()
570 case 0x2e8: outb(0x15, cfg_base+1); break; in nsc_ircc_init_108()
571 case 0x3f8: outb(0x16, cfg_base+1); break; in nsc_ircc_init_108()
572 case 0x2f8: outb(0x17, cfg_base+1); break; in nsc_ircc_init_108()
587 outb(CFG_108_CSRT, cfg_base); in nsc_ircc_init_108()
590 case 0: outb(0x08+temp, cfg_base+1); break; in nsc_ircc_init_108()
591 case 1: outb(0x10+temp, cfg_base+1); break; in nsc_ircc_init_108()
592 case 3: outb(0x18+temp, cfg_base+1); break; in nsc_ircc_init_108()
596 outb(CFG_108_MCTL, cfg_base); /* Mode Control Register (MCTL) */ in nsc_ircc_init_108()
597 outb(0x03, cfg_base+1); /* Enable device */ in nsc_ircc_init_108()
614 outb(CFG_108_BAIC, cfg_base); in nsc_ircc_probe_108()
636 outb(CFG_108_CSRT, cfg_base); in nsc_ircc_probe_108()
685 outb(CFG_108_MCTL, cfg_base); in nsc_ircc_probe_108()
722 outb(CFG_338_FER, cfg_base); in nsc_ircc_probe_338()
728 outb(CFG_338_PNP0, cfg_base); in nsc_ircc_probe_338()
734 outb(0x46, cfg_base); in nsc_ircc_probe_338()
737 outb(0x47, cfg_base); in nsc_ircc_probe_338()
743 outb(CFG_338_FAR, cfg_base); in nsc_ircc_probe_338()
793 outb(CFG_338_PNP1, cfg_base); in nsc_ircc_probe_338()
799 outb(CFG_338_PNP3, cfg_base); in nsc_ircc_probe_338()
805 outb(CFG_338_PTR, cfg_base); in nsc_ircc_probe_338()
841 outb(CFG_39X_LDN, cfg_base); in nsc_ircc_init_39x()
842 outb(0x02, cfg_base+1); in nsc_ircc_init_39x()
847 outb(CFG_39X_ACT, cfg_base); in nsc_ircc_init_39x()
852 outb(CFG_39X_SIOCF1, cfg_base); in nsc_ircc_init_39x()
853 outb(0x01, cfg_base+1); in nsc_ircc_init_39x()
859 outb(CFG_39X_SPC, cfg_base); in nsc_ircc_init_39x()
860 outb(0x82, cfg_base+1); in nsc_ircc_init_39x()
885 outb(CFG_39X_LDN, cfg_base); in nsc_ircc_probe_39x()
886 outb(0x02, cfg_base+1); in nsc_ircc_probe_39x()
889 outb(CFG_39X_BASEH, cfg_base); in nsc_ircc_probe_39x()
891 outb(CFG_39X_BASEL, cfg_base); in nsc_ircc_probe_39x()
895 outb(CFG_39X_IRQNUM, cfg_base); in nsc_ircc_probe_39x()
897 outb(CFG_39X_IRQSEL, cfg_base); in nsc_ircc_probe_39x()
901 outb(CFG_39X_DMA0, cfg_base); in nsc_ircc_probe_39x()
903 outb(CFG_39X_DMA1, cfg_base); in nsc_ircc_probe_39x()
907 outb(CFG_39X_ACT, cfg_base); in nsc_ircc_probe_39x()
910 outb(CFG_39X_SPC, cfg_base); in nsc_ircc_probe_39x()
919 outb(CFG_39X_ACT, cfg_base); in nsc_ircc_probe_39x()
924 outb(CFG_39X_SIOCF1, cfg_base); in nsc_ircc_probe_39x()
925 outb(0x01, cfg_base+1); in nsc_ircc_probe_39x()
931 outb(CFG_39X_SPC, cfg_base); in nsc_ircc_probe_39x()
932 outb(0x82, cfg_base+1); in nsc_ircc_probe_39x()
1006 outb(ECR1_EXT_SL, iobase+ECR1); in nsc_ircc_setup()
1011 outb(FCR_RXTH|FCR_TXTH|FCR_TXSR|FCR_RXSR|FCR_FIFO_EN, iobase+FCR); in nsc_ircc_setup()
1013 outb(0x03, iobase+LCR); /* 8 bit word length */ in nsc_ircc_setup()
1014 outb(MCR_SIR, iobase+MCR); /* Start at SIR-mode, also clears LSR*/ in nsc_ircc_setup()
1018 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2); in nsc_ircc_setup()
1022 outb(0x02, iobase+4); in nsc_ircc_setup()
1026 outb(0x20, iobase+0); /* Set 32 bits FIR CRC */ in nsc_ircc_setup()
1027 outb(0x0a, iobase+1); /* Set MIR pulse width */ in nsc_ircc_setup()
1028 outb(0x0d, iobase+2); /* Set SIR pulse width to 1.6us */ in nsc_ircc_setup()
1029 outb(0x2a, iobase+4); /* Set beginning frag, and preamble length */ in nsc_ircc_setup()
1033 outb(IER_RXHDL_IE, iobase+IER); in nsc_ircc_setup()
1056 outb(0x00, iobase+7); in nsc_ircc_read_dongle_id()
1071 outb(bank, iobase+BSR); in nsc_ircc_read_dongle_id()
1125 outb(0x28, iobase+7); /* Set irsl[0-2] as output */ in nsc_ircc_init_dongle_interface()
1138 outb(0x48, iobase+7); in nsc_ircc_init_dongle_interface()
1141 outb(0x28, iobase+7); /* Set irsl[0-2] as output */ in nsc_ircc_init_dongle_interface()
1148 outb(0x62, iobase+MCR); in nsc_ircc_init_dongle_interface()
1156 outb(0x00, iobase+4); in nsc_ircc_init_dongle_interface()
1159 outb(bank, iobase+BSR); in nsc_ircc_init_dongle_interface()
1208 outb(0x00, iobase+4); in nsc_ircc_change_dongle_speed()
1210 outb(0x01, iobase+4); in nsc_ircc_change_dongle_speed()
1213 outb(0x01, iobase+4); in nsc_ircc_change_dongle_speed()
1218 outb(0x81, iobase+4); in nsc_ircc_change_dongle_speed()
1219 outb(0x80, iobase+4); in nsc_ircc_change_dongle_speed()
1221 outb(0x00, iobase+4); in nsc_ircc_change_dongle_speed()
1238 outb(0x62, iobase+MCR); in nsc_ircc_change_dongle_speed()
1244 outb(bank, iobase+BSR); in nsc_ircc_change_dongle_speed()
1276 outb(0, iobase+IER); in nsc_ircc_change_speed()
1281 outb(0x00, iobase+BGDH); in nsc_ircc_change_speed()
1283 case 9600: outb(0x0c, iobase+BGDL); break; in nsc_ircc_change_speed()
1284 case 19200: outb(0x06, iobase+BGDL); break; in nsc_ircc_change_speed()
1285 case 38400: outb(0x03, iobase+BGDL); break; in nsc_ircc_change_speed()
1286 case 57600: outb(0x02, iobase+BGDL); break; in nsc_ircc_change_speed()
1287 case 115200: outb(0x01, iobase+BGDL); break; in nsc_ircc_change_speed()
1292 outb(inb(iobase+4) | 0x04, iobase+4); in nsc_ircc_change_speed()
1314 outb(mcr | MCR_TX_DFR, iobase+MCR); in nsc_ircc_change_speed()
1321 outb(0x00, iobase+FCR); in nsc_ircc_change_speed()
1322 outb(FCR_FIFO_EN, iobase+FCR); in nsc_ircc_change_speed()
1323 outb(FCR_RXTH| /* Set Rx FIFO threshold */ in nsc_ircc_change_speed()
1332 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2); in nsc_ircc_change_speed()
1347 outb(ier, iobase+IER); in nsc_ircc_change_speed()
1350 outb(bank, iobase+BSR); in nsc_ircc_change_speed()
1422 outb(IER_TXLDL_IE, iobase+IER); in nsc_ircc_hard_xmit_sir()
1425 outb(bank, iobase+BSR); in nsc_ircc_hard_xmit_sir()
1523 outb(mtt & 0xff, iobase+TMRL); in nsc_ircc_hard_xmit_fir()
1524 outb((mtt >> 8) & 0x0f, iobase+TMRH); in nsc_ircc_hard_xmit_fir()
1527 outb(IRCR1_TMR_EN, iobase+IRCR1); in nsc_ircc_hard_xmit_fir()
1532 outb(IER_TMR_IE, iobase+IER); in nsc_ircc_hard_xmit_fir()
1542 outb(IER_DMA_IE, iobase+IER); in nsc_ircc_hard_xmit_fir()
1554 outb(bank, iobase+BSR); in nsc_ircc_hard_xmit_fir()
1578 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); in nsc_ircc_dma_xmit()
1584 outb(ECR1_DMASWP|ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1); in nsc_ircc_dma_xmit()
1594 outb(inb(iobase+MCR)|MCR_TX_DFR|MCR_DMA_EN|MCR_IR_PLS, iobase+MCR); in nsc_ircc_dma_xmit()
1597 outb(bsr, iobase+BSR); in nsc_ircc_dma_xmit()
1627 outb(buf[actual++], iobase+TXD); in nsc_ircc_pio_write()
1634 outb(bank, iobase+BSR); in nsc_ircc_pio_write()
1659 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); in nsc_ircc_dma_xmit_complete()
1667 outb(ASCR_TXUR, iobase+ASCR); in nsc_ircc_dma_xmit_complete()
1697 outb(bank, iobase+BSR); in nsc_ircc_dma_xmit_complete()
1725 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); in nsc_ircc_dma_receive()
1729 outb(ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1); in nsc_ircc_dma_receive()
1736 outb(FCR_RXSR|FCR_FIFO_EN, iobase+FCR); in nsc_ircc_dma_receive()
1746 outb(inb(iobase+MCR)|MCR_DMA_EN, iobase+MCR); in nsc_ircc_dma_receive()
1749 outb(bsr, iobase+BSR); in nsc_ircc_dma_receive()
1849 outb(0x02, iobase+TMRL); /* x 125 us */ in nsc_ircc_dma_receive_complete()
1850 outb(0x00, iobase+TMRH); in nsc_ircc_dma_receive_complete()
1853 outb(IRCR1_TMR_EN, iobase+IRCR1); in nsc_ircc_dma_receive_complete()
1856 outb(bank, iobase+BSR); in nsc_ircc_dma_receive_complete()
1874 outb(bank, iobase+BSR); in nsc_ircc_dma_receive_complete()
1907 outb(bank, iobase+BSR); in nsc_ircc_dma_receive_complete()
2023 outb(0, iobase+IRCR1); in nsc_ircc_fir_interrupt()
2027 outb(ASCR_CTE, iobase+ASCR); in nsc_ircc_fir_interrupt()
2075 outb(bank, iobase+BSR); in nsc_ircc_fir_interrupt()
2103 outb(0, iobase+IER); /* Disable interrupts */ in nsc_ircc_interrupt()
2113 outb(self->ier, iobase+IER); /* Restore interrupts */ in nsc_ircc_interrupt()
2114 outb(bsr, iobase+BSR); /* Restore bank register */ in nsc_ircc_interrupt()
2147 outb(bank, iobase+BSR); in nsc_ircc_is_receiving()
2198 outb(IER_LS_IE | IER_RXHDL_IE, iobase+IER); in nsc_ircc_net_open()
2201 outb(bank, iobase+BSR); in nsc_ircc_net_open()
2253 outb(0, iobase+IER); in nsc_ircc_net_close()
2259 outb(bank, iobase+BSR); in nsc_ircc_net_close()
2333 outb(0, iobase+IER); in nsc_ircc_suspend()
2336 outb(bank, iobase+BSR); in nsc_ircc_suspend()