308 	outb(0, IER(iobase));  in fpga_reset()
309 	outb(LCR_DLAB | LCR_BIT5, LCR(iobase));  in fpga_reset()
310 	outb(1, DLL(iobase));  in fpga_reset()
311 	outb(0, DLM(iobase));  in fpga_reset()
313 	outb(LCR_BIT5, LCR(iobase));  in fpga_reset()
317 	outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));  in fpga_reset()
320 	outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));  in fpga_reset()
336 		outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));  in fpga_write()
338 		outb(0xfc, THR(iobase));  in fpga_write()
480 	outb(0, IER(dev->base_addr));  in yam_set_uart()
481 	outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr));  in yam_set_uart()
482 	outb(divisor, DLL(dev->base_addr));  in yam_set_uart()
483 	outb(0, DLM(dev->base_addr));  in yam_set_uart()
484 	outb(LCR_BIT8, LCR(dev->base_addr));  in yam_set_uart()
485 	outb(PTT_OFF, MCR(dev->base_addr));  in yam_set_uart()
486 	outb(0x00, FCR(dev->base_addr));  in yam_set_uart()
495 	outb(ENABLE_RTXINT, IER(dev->base_addr));  in yam_set_uart()
517 	outb(b1 | 0x10, MCR(iobase));	/* loopback mode */  in yam_check_uart()
519 	outb(0x1a, MCR(iobase));  in yam_check_uart()
521 	outb(b1, MCR(iobase));		/* restore old values */  in yam_check_uart()
522 	outb(b2, MSR(iobase));  in yam_check_uart()
527 	outb(0x01, FCR(iobase));	/* enable FIFOs */  in yam_check_uart()
530 		outb(0x5a, SCR(iobase));  in yam_check_uart()
532 		outb(0xa5, SCR(iobase));  in yam_check_uart()
587 	outb(PTT_ON, MCR(dev->base_addr));  in ptt_on()
592 	outb(PTT_OFF, MCR(dev->base_addr));  in ptt_off()
701 		outb(b, THR(dev->base_addr));  in yam_tx_byte()
712 		outb(yp->tx_crcl, THR(dev->base_addr));  in yam_tx_byte()
716 		outb(chktabh[yp->tx_crch] ^ 0xFF, THR(dev->base_addr));  in yam_tx_byte()
893 	outb(0, IER(dev->base_addr));  in yam_open()
936 	outb(0, IER(dev->base_addr));  in yam_close()
937 	outb(1, MCR(dev->base_addr));  in yam_close()