162 	__raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK,  in xemaclite_enable_interrupts()
166 	__raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);  in xemaclite_enable_interrupts()
169 	__raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);  in xemaclite_enable_interrupts()
184 	__raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);  in xemaclite_disable_interrupts()
188 	__raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),  in xemaclite_disable_interrupts()
193 	__raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),  in xemaclite_disable_interrupts()
350 	__raw_writel((byte_count & XEL_TPLR_LENGTH_MASK),  in xemaclite_send_data()
359 	__raw_writel(reg_data, addr + XEL_TSR_OFFSET);  in xemaclite_send_data()
441 	__raw_writel(reg_data, addr + XEL_RSR_OFFSET);  in xemaclite_recv_data()
468 	__raw_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);  in xemaclite_update_address()
472 	__raw_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);  in xemaclite_update_address()
658 		__raw_writel(tx_status, base_addr + XEL_TSR_OFFSET);  in xemaclite_interrupt()
669 		__raw_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +  in xemaclite_interrupt()
740 	__raw_writel(XEL_MDIOADDR_OP_MASK |  in xemaclite_mdio_read()
743 	__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,  in xemaclite_mdio_read()
787 	__raw_writel(~XEL_MDIOADDR_OP_MASK &  in xemaclite_mdio_write()
790 	__raw_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);  in xemaclite_mdio_write()
791 	__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,  in xemaclite_mdio_write()
839 	__raw_writel(XEL_MDIOCTRL_MDIOEN_MASK,  in xemaclite_mdio_setup()
1144 	__raw_writel(0, lp->base_addr + XEL_TSR_OFFSET);  in xemaclite_of_probe()
1145 	__raw_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);  in xemaclite_of_probe()