275 #define IOSYNC	do { ioread8(ioaddr + StationAddr); } while (0)
487 #define BYTE_REG_BITS_ON(x, p)      do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
491 #define BYTE_REG_BITS_IS_ON(x, p)   (ioread8((p)) & (x))
495 #define BYTE_REG_BITS_OFF(x, p)     do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
499 #define BYTE_REG_BITS_SET(x, m, p)   do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
533 		bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask);  in rhine_wait_bit()
563 		intr_status |= ioread8(ioaddr + IntrStatus2) << 16;  in rhine_get_events()
589 		iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);  in rhine_power_init()
601 		wolstat = ioread8(ioaddr + PwrcsrSet);  in rhine_power_init()
603 			wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;  in rhine_power_init()
646 	if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {  in rhine_chip_reset()
657 	cmd1 = ioread8(ioaddr + ChipCmd1);  in rhine_chip_reset()
730 		iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);  in rhine_reload_eeprom()
842 			if (ioread8(ioaddr + ChipCmd) & CmdTxOn)  in rhine_napipoll()
945 		dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);  in rhine_init_one_common()
957 		phy_id = ioread8(ioaddr + 0x6C);  in rhine_init_one_common()
1375 	    iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,  in rhine_check_media()
1378 	    iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,  in rhine_check_media()
1875 	iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,  in rhine_start_tx()
2179 		iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,  in rhine_restart_tx()
2186 		iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,  in rhine_restart_tx()
2503 		iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);  in rhine_shutdown_pci()
2518 		iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);  in rhine_shutdown_pci()
2524 		iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);  in rhine_shutdown_pci()