Lines Matching refs:ioaddr
275 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
529 void __iomem *ioaddr = rp->base; in rhine_wait_bit() local
533 bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask); in rhine_wait_bit()
557 void __iomem *ioaddr = rp->base; in rhine_get_events() local
560 intr_status = ioread16(ioaddr + IntrStatus); in rhine_get_events()
563 intr_status |= ioread8(ioaddr + IntrStatus2) << 16; in rhine_get_events()
569 void __iomem *ioaddr = rp->base; in rhine_ack_events() local
572 iowrite8(mask >> 16, ioaddr + IntrStatus2); in rhine_ack_events()
573 iowrite16(mask, ioaddr + IntrStatus); in rhine_ack_events()
584 void __iomem *ioaddr = rp->base; in rhine_power_init() local
589 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW); in rhine_power_init()
592 iowrite8(0x80, ioaddr + WOLcgClr); in rhine_power_init()
595 iowrite8(0xFF, ioaddr + WOLcrClr); in rhine_power_init()
598 iowrite8(0x03, ioaddr + WOLcrClr1); in rhine_power_init()
601 wolstat = ioread8(ioaddr + PwrcsrSet); in rhine_power_init()
603 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8; in rhine_power_init()
606 iowrite8(0xFF, ioaddr + PwrcsrClr); in rhine_power_init()
608 iowrite8(0x03, ioaddr + PwrcsrClr1); in rhine_power_init()
640 void __iomem *ioaddr = rp->base; in rhine_chip_reset() local
643 iowrite8(Cmd1Reset, ioaddr + ChipCmd1); in rhine_chip_reset()
646 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) { in rhine_chip_reset()
651 iowrite8(0x40, ioaddr + MiscCmd); in rhine_chip_reset()
657 cmd1 = ioread8(ioaddr + ChipCmd1); in rhine_chip_reset()
680 void __iomem *ioaddr, in verify_mmio() argument
690 unsigned char b = readb(ioaddr+reg); in verify_mmio()
710 void __iomem *ioaddr = rp->base; in rhine_reload_eeprom() local
730 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA); in rhine_reload_eeprom()
749 void __iomem *ioaddr = rp->base; in rhine_kick_tx_threshold() local
752 BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig); in rhine_kick_tx_threshold()
786 void __iomem *ioaddr = rp->base; in rhine_update_rx_crc_and_missed_errord() local
789 stats->rx_crc_errors += ioread16(ioaddr + RxCRCErrs); in rhine_update_rx_crc_and_missed_errord()
790 stats->rx_missed_errors += ioread16(ioaddr + RxMissed); in rhine_update_rx_crc_and_missed_errord()
798 iowrite32(0, ioaddr + RxMissed); in rhine_update_rx_crc_and_missed_errord()
799 ioread16(ioaddr + RxCRCErrs); in rhine_update_rx_crc_and_missed_errord()
800 ioread16(ioaddr + RxMissed); in rhine_update_rx_crc_and_missed_errord()
827 void __iomem *ioaddr = rp->base; in rhine_napipoll() local
842 if (ioread8(ioaddr + ChipCmd) & CmdTxOn) in rhine_napipoll()
865 iowrite16(enable_mask, ioaddr + IntrEnable); in rhine_napipoll()
906 long pioaddr, void __iomem *ioaddr, int irq) in rhine_init_one_common() argument
931 rp->base = ioaddr; in rhine_init_one_common()
945 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i); in rhine_init_one_common()
957 phy_id = ioread8(ioaddr + 0x6C); in rhine_init_one_common()
1000 name, (long)ioaddr, dev->dev_addr, rp->irq); in rhine_init_one_common()
1043 void __iomem *ioaddr; in rhine_init_one_pci() local
1098 ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size); in rhine_init_one_pci()
1099 if (!ioaddr) { in rhine_init_one_pci()
1109 rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks); in rhine_init_one_pci()
1114 pioaddr, ioaddr, pdev->irq); in rhine_init_one_pci()
1119 pci_iounmap(pdev, ioaddr); in rhine_init_one_pci()
1134 void __iomem *ioaddr; in rhine_init_one_platform() local
1141 ioaddr = devm_ioremap_resource(&pdev->dev, res); in rhine_init_one_platform()
1142 if (IS_ERR(ioaddr)) in rhine_init_one_platform()
1143 return PTR_ERR(ioaddr); in rhine_init_one_platform()
1154 (long)ioaddr, ioaddr, irq); in rhine_init_one_platform()
1369 void __iomem *ioaddr = rp->base; in rhine_check_media() local
1375 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex, in rhine_check_media()
1376 ioaddr + ChipCmd1); in rhine_check_media()
1378 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex, in rhine_check_media()
1379 ioaddr + ChipCmd1); in rhine_check_media()
1411 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr) in rhine_set_cam() argument
1415 iowrite8(CAMC_CAMEN, ioaddr + CamCon); in rhine_set_cam()
1421 iowrite8((u8) idx, ioaddr + CamAddr); in rhine_set_cam()
1424 iowrite8(*addr, ioaddr + MulticastFilter0 + i); in rhine_set_cam()
1428 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); in rhine_set_cam()
1431 iowrite8(0, ioaddr + CamCon); in rhine_set_cam()
1442 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr) in rhine_set_vlan_cam() argument
1444 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); in rhine_set_vlan_cam()
1450 iowrite8((u8) idx, ioaddr + CamAddr); in rhine_set_vlan_cam()
1452 iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6); in rhine_set_vlan_cam()
1456 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); in rhine_set_vlan_cam()
1459 iowrite8(0, ioaddr + CamCon); in rhine_set_vlan_cam()
1469 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask) in rhine_set_cam_mask() argument
1471 iowrite8(CAMC_CAMEN, ioaddr + CamCon); in rhine_set_cam_mask()
1475 iowrite32(mask, ioaddr + CamMask); in rhine_set_cam_mask()
1478 iowrite8(0, ioaddr + CamCon); in rhine_set_cam_mask()
1488 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask) in rhine_set_vlan_cam_mask() argument
1490 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); in rhine_set_vlan_cam_mask()
1494 iowrite32(mask, ioaddr + CamMask); in rhine_set_vlan_cam_mask()
1497 iowrite8(0, ioaddr + CamCon); in rhine_set_vlan_cam_mask()
1510 void __iomem *ioaddr = rp->base; in rhine_init_cam_filter() local
1513 rhine_set_vlan_cam_mask(ioaddr, 0); in rhine_init_cam_filter()
1514 rhine_set_cam_mask(ioaddr, 0); in rhine_init_cam_filter()
1517 BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig); in rhine_init_cam_filter()
1518 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1); in rhine_init_cam_filter()
1530 void __iomem *ioaddr = rp->base; in rhine_update_vcam() local
1536 rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid); in rhine_update_vcam()
1541 rhine_set_vlan_cam_mask(ioaddr, vCAMmask); in rhine_update_vcam()
1569 void __iomem *ioaddr = rp->base; in init_registers() local
1573 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i); in init_registers()
1576 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */ in init_registers()
1578 iowrite8(0x20, ioaddr + TxConfig); in init_registers()
1582 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr); in init_registers()
1583 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr); in init_registers()
1592 iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable); in init_registers()
1595 ioaddr + ChipCmd); in init_registers()
1602 void __iomem *ioaddr = rp->base; in rhine_enable_linkmon() local
1604 iowrite8(0, ioaddr + MIICmd); in rhine_enable_linkmon()
1605 iowrite8(MII_BMSR, ioaddr + MIIRegAddr); in rhine_enable_linkmon()
1606 iowrite8(0x80, ioaddr + MIICmd); in rhine_enable_linkmon()
1610 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr); in rhine_enable_linkmon()
1616 void __iomem *ioaddr = rp->base; in rhine_disable_linkmon() local
1618 iowrite8(0, ioaddr + MIICmd); in rhine_disable_linkmon()
1621 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR in rhine_disable_linkmon()
1627 iowrite8(0x80, ioaddr + MIICmd); in rhine_disable_linkmon()
1632 iowrite8(0, ioaddr + MIICmd); in rhine_disable_linkmon()
1643 void __iomem *ioaddr = rp->base; in mdio_read() local
1649 iowrite8(phy_id, ioaddr + MIIPhyAddr); in mdio_read()
1650 iowrite8(regnum, ioaddr + MIIRegAddr); in mdio_read()
1651 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */ in mdio_read()
1653 result = ioread16(ioaddr + MIIData); in mdio_read()
1662 void __iomem *ioaddr = rp->base; in mdio_write() local
1667 iowrite8(phy_id, ioaddr + MIIPhyAddr); in mdio_write()
1668 iowrite8(regnum, ioaddr + MIIRegAddr); in mdio_write()
1669 iowrite16(value, ioaddr + MIIData); in mdio_write()
1670 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */ in mdio_write()
1696 void __iomem *ioaddr = rp->base; in rhine_open() local
1719 __func__, ioread16(ioaddr + ChipCmd), in rhine_open()
1772 void __iomem *ioaddr = rp->base; in rhine_tx_timeout() local
1775 ioread16(ioaddr + IntrStatus), in rhine_tx_timeout()
1791 void __iomem *ioaddr = rp->base; in rhine_start_tx() local
1872 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake); in rhine_start_tx()
1875 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, in rhine_start_tx()
1876 ioaddr + ChipCmd1); in rhine_start_tx()
2163 void __iomem *ioaddr = rp->base; in rhine_restart_tx() local
2177 ioaddr + TxRingPtr); in rhine_restart_tx()
2179 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn, in rhine_restart_tx()
2180 ioaddr + ChipCmd); in rhine_restart_tx()
2184 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake); in rhine_restart_tx()
2186 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, in rhine_restart_tx()
2187 ioaddr + ChipCmd1); in rhine_restart_tx()
2255 void __iomem *ioaddr = rp->base; in rhine_set_rx_mode() local
2262 iowrite32(0xffffffff, ioaddr + MulticastFilter0); in rhine_set_rx_mode()
2263 iowrite32(0xffffffff, ioaddr + MulticastFilter1); in rhine_set_rx_mode()
2267 iowrite32(0xffffffff, ioaddr + MulticastFilter0); in rhine_set_rx_mode()
2268 iowrite32(0xffffffff, ioaddr + MulticastFilter1); in rhine_set_rx_mode()
2275 rhine_set_cam(ioaddr, i, ha->addr); in rhine_set_rx_mode()
2279 rhine_set_cam_mask(ioaddr, mCAMmask); in rhine_set_rx_mode()
2287 iowrite32(mc_filter[0], ioaddr + MulticastFilter0); in rhine_set_rx_mode()
2288 iowrite32(mc_filter[1], ioaddr + MulticastFilter1); in rhine_set_rx_mode()
2293 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1); in rhine_set_rx_mode()
2295 BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1); in rhine_set_rx_mode()
2297 BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig); in rhine_set_rx_mode()
2426 void __iomem *ioaddr = rp->base; in rhine_close() local
2433 ioread16(ioaddr + ChipCmd)); in rhine_close()
2436 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig); in rhine_close()
2441 iowrite16(CmdStop, ioaddr + ChipCmd); in rhine_close()
2484 void __iomem *ioaddr = rp->base; in rhine_shutdown_pci() local
2493 iowrite8(0x04, ioaddr + WOLcgClr); in rhine_shutdown_pci()
2498 iowrite8(WOLmagic, ioaddr + WOLcrSet); in rhine_shutdown_pci()
2503 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA); in rhine_shutdown_pci()
2507 iowrite8(WOLbmcast, ioaddr + WOLcgSet); in rhine_shutdown_pci()
2510 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet); in rhine_shutdown_pci()
2513 iowrite8(WOLucast, ioaddr + WOLcrSet); in rhine_shutdown_pci()
2517 iowrite8(0x01, ioaddr + PwcfgSet); in rhine_shutdown_pci()
2518 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW); in rhine_shutdown_pci()
2524 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW); in rhine_shutdown_pci()