963 	u32 phy   = priv->phy[priv->phy_num];  in tlan_ioctl()  local
970 		data->phy_id = phy;  in tlan_ioctl()
1705 	u32		phy;  in tlan_handle_status_check()  local
1723 		phy = priv->phy[priv->phy_num];  in tlan_handle_status_check()
1732 			tlan_mii_read_reg(dev, phy, TLAN_TLPHY_STS, &tlphy_sts);  in tlan_handle_status_check()
1733 			tlan_mii_read_reg(dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl);  in tlan_handle_status_check()
1737 				tlan_mii_write_reg(dev, phy, TLAN_TLPHY_CTL,  in tlan_handle_status_check()
1742 				tlan_mii_write_reg(dev, phy, TLAN_TLPHY_CTL,  in tlan_handle_status_check()
2262 	u32		phy;  in tlan_finish_reset()  local
2271 	phy = priv->phy[priv->phy_num];  in tlan_finish_reset()
2282 	tlan_mii_read_reg(dev, phy, MII_GEN_ID_HI, &tlphy_id1);  in tlan_finish_reset()
2283 	tlan_mii_read_reg(dev, phy, MII_GEN_ID_LO, &tlphy_id2);  in tlan_finish_reset()
2290 		tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_finish_reset()
2292 		tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_finish_reset()
2297 				tlan_mii_read_reg(dev, phy, MII_AN_LPA,  in tlan_finish_reset()
2299 				tlan_mii_read_reg(dev, phy, TLAN_TLPHY_PAR,  in tlan_finish_reset()
2330 		tlan_mii_read_reg(dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl);  in tlan_finish_reset()
2332 		tlan_mii_write_reg(dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);  in tlan_finish_reset()
2429 	u16 i, data0, data1, data2, data3, phy;  in tlan_phy_print()  local
2431 	phy = priv->phy[priv->phy_num];  in tlan_phy_print()
2435 	} else if (phy <= TLAN_PHY_MAX_ADDR) {  in tlan_phy_print()
2436 		netdev_info(dev, "PHY 0x%02x\n", phy);  in tlan_phy_print()
2439 			tlan_mii_read_reg(dev, phy, i, &data0);  in tlan_phy_print()
2440 			tlan_mii_read_reg(dev, phy, i + 1, &data1);  in tlan_phy_print()
2441 			tlan_mii_read_reg(dev, phy, i + 2, &data2);  in tlan_phy_print()
2442 			tlan_mii_read_reg(dev, phy, i + 3, &data3);  in tlan_phy_print()
2478 	u32		phy;  in tlan_phy_detect()  local
2488 		priv->phy[0] = TLAN_PHY_MAX_ADDR;  in tlan_phy_detect()
2490 		priv->phy[0] = TLAN_PHY_NONE;  in tlan_phy_detect()
2492 	priv->phy[1] = TLAN_PHY_NONE;  in tlan_phy_detect()
2493 	for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {  in tlan_phy_detect()
2494 		tlan_mii_read_reg(dev, phy, MII_GEN_CTL, &control);  in tlan_phy_detect()
2495 		tlan_mii_read_reg(dev, phy, MII_GEN_ID_HI, &hi);  in tlan_phy_detect()
2496 		tlan_mii_read_reg(dev, phy, MII_GEN_ID_LO, &lo);  in tlan_phy_detect()
2501 				 phy, control, hi, lo);  in tlan_phy_detect()
2502 			if ((priv->phy[1] == TLAN_PHY_NONE) &&  in tlan_phy_detect()
2503 			    (phy != TLAN_PHY_MAX_ADDR)) {  in tlan_phy_detect()
2504 				priv->phy[1] = phy;  in tlan_phy_detect()
2509 	if (priv->phy[1] != TLAN_PHY_NONE)  in tlan_phy_detect()
2511 	else if (priv->phy[0] != TLAN_PHY_NONE)  in tlan_phy_detect()
2529 	tlan_mii_write_reg(dev, priv->phy[priv->phy_num], MII_GEN_CTL, value);  in tlan_phy_power_down()
2530 	if ((priv->phy_num == 0) && (priv->phy[1] != TLAN_PHY_NONE)) {  in tlan_phy_power_down()
2535 		tlan_mii_write_reg(dev, priv->phy[1], MII_GEN_CTL, value);  in tlan_phy_power_down()
2557 	tlan_mii_write_reg(dev, priv->phy[priv->phy_num], MII_GEN_CTL, value);  in tlan_phy_power_up()
2573 	u16		phy;  in tlan_phy_reset()  local
2577 	phy = priv->phy[priv->phy_num];  in tlan_phy_reset()
2582 	tlan_mii_write_reg(dev, phy, MII_GEN_CTL, value);  in tlan_phy_reset()
2584 		tlan_mii_read_reg(dev, phy, MII_GEN_CTL, &value);  in tlan_phy_reset()
2608 	u16		phy;  in tlan_phy_start_link()  local
2612 	phy = priv->phy[priv->phy_num];  in tlan_phy_start_link()
2614 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_phy_start_link()
2615 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &ability);  in tlan_phy_start_link()
2622 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x0000);  in tlan_phy_start_link()
2626 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x0100);  in tlan_phy_start_link()
2629 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x2000);  in tlan_phy_start_link()
2633 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x2100);  in tlan_phy_start_link()
2637 			tlan_mii_write_reg(dev, phy, MII_AN_ADV,  in tlan_phy_start_link()
2640 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x1000);  in tlan_phy_start_link()
2642 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x1200);  in tlan_phy_start_link()
2664 		tlan_mii_read_reg(dev, phy, TLAN_TLPHY_CTL, &tctl);  in tlan_phy_start_link()
2676 		tlan_mii_write_reg(dev, phy, MII_GEN_CTL, control);  in tlan_phy_start_link()
2677 		tlan_mii_write_reg(dev, phy, TLAN_TLPHY_CTL, tctl);  in tlan_phy_start_link()
2696 	u16		phy;  in tlan_phy_finish_auto_neg()  local
2699 	phy = priv->phy[priv->phy_num];  in tlan_phy_finish_auto_neg()
2701 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_phy_finish_auto_neg()
2703 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_phy_finish_auto_neg()
2714 	tlan_mii_read_reg(dev, phy, MII_AN_ADV, &an_adv);  in tlan_phy_finish_auto_neg()
2715 	tlan_mii_read_reg(dev, phy, MII_AN_LPA, &an_lpa);  in tlan_phy_finish_auto_neg()
2734 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL,  in tlan_phy_finish_auto_neg()
2738 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL,  in tlan_phy_finish_auto_neg()
2772 	u16     phy;  in tlan_phy_monitor()  local
2775 	phy = priv->phy[priv->phy_num];  in tlan_phy_monitor()
2778 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &phy_status);  in tlan_phy_monitor()
2793 				tlan_mii_write_reg(dev, priv->phy[0],  in tlan_phy_monitor()
2854 tlan_mii_read_reg(struct net_device *dev, u16 phy, u16 reg, u16 *val)  in tlan_mii_read_reg()  argument
2879 	tlan_mii_send_data(dev->base_addr, phy, 5);	/* device #      */  in tlan_mii_read_reg()
3026 tlan_mii_write_reg(struct net_device *dev, u16 phy, u16 reg, u16 val)  in tlan_mii_write_reg()  argument
3047 	tlan_mii_send_data(dev->base_addr, phy, 5);	/* device #      */  in tlan_mii_write_reg()