655 	void __iomem			*switch_regs;  member
1777 	val = readl(GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));  in gbe_stats_mod_visible_ver14()
1793 	writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));  in gbe_stats_mod_visible_ver14()
2423 	reg = readl(GBE_REG_ADDR(gbe_dev, switch_regs, id_ver));  in gbe_open()
2447 	writel(0, GBE_REG_ADDR(gbe_dev, switch_regs, ptype));  in gbe_open()
2450 	writel(GBE_CTL_P0_ENABLE, GBE_REG_ADDR(gbe_dev, switch_regs, control));  in gbe_open()
2453 	writel(gbe_dev->stats_en_mask, GBE_REG_ADDR(gbe_dev, switch_regs,  in gbe_open()
2542 	slave->port_regs = gbe_dev->switch_regs + port_reg_ofs +  in init_slave()
2544 	slave->emac_regs = gbe_dev->switch_regs + emac_reg_ofs +  in init_slave()
2741 	gbe_dev->switch_regs = regs;  in set_xgbe_ethss10_priv()
2786 		gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +  in set_xgbe_ethss10_priv()
2789 	gbe_dev->ale_reg = gbe_dev->switch_regs + XGBE10_ALE_OFFSET;  in set_xgbe_ethss10_priv()
2800 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);  in set_xgbe_ethss10_priv()
2801 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, control);  in set_xgbe_ethss10_priv()
2802 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);  in set_xgbe_ethss10_priv()
2803 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);  in set_xgbe_ethss10_priv()
2804 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);  in set_xgbe_ethss10_priv()
2875 	gbe_dev->switch_regs = regs;  in set_gbe_ethss14_priv()
2900 	gbe_dev->host_port_regs = gbe_dev->switch_regs + GBE13_HOST_PORT_OFFSET;  in set_gbe_ethss14_priv()
2908 			gbe_dev->switch_regs + GBE13_HW_STATS_OFFSET +  in set_gbe_ethss14_priv()
2912 	gbe_dev->ale_reg = gbe_dev->switch_regs + GBE13_ALE_OFFSET;  in set_gbe_ethss14_priv()
2922 	GBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);  in set_gbe_ethss14_priv()
2923 	GBE_SET_REG_OFS(gbe_dev, switch_regs, control);  in set_gbe_ethss14_priv()
2924 	GBE_SET_REG_OFS(gbe_dev, switch_regs, soft_reset);  in set_gbe_ethss14_priv()
2925 	GBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);  in set_gbe_ethss14_priv()
2926 	GBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);  in set_gbe_ethss14_priv()
2927 	GBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);  in set_gbe_ethss14_priv()
2984 	gbe_dev->switch_regs = regs;  in set_gbenu_ethss_priv()
2995 	gbe_dev->host_port_regs = gbe_dev->switch_regs + GBENU_HOST_PORT_OFFSET;  in set_gbenu_ethss_priv()
2998 		gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +  in set_gbenu_ethss_priv()
3001 	gbe_dev->ale_reg = gbe_dev->switch_regs + GBENU_ALE_OFFSET;  in set_gbenu_ethss_priv()
3011 	GBENU_SET_REG_OFS(gbe_dev, switch_regs, id_ver);  in set_gbenu_ethss_priv()
3012 	GBENU_SET_REG_OFS(gbe_dev, switch_regs, control);  in set_gbenu_ethss_priv()
3013 	GBENU_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);  in set_gbenu_ethss_priv()
3014 	GBENU_SET_REG_OFS(gbe_dev, switch_regs, ptype);  in set_gbenu_ethss_priv()