136 #define dma_reg_write(ctlr, ofs, v)	__raw_writel(v, (ctlr)->dmaregs + (ofs))  macro
307 		dma_reg_write(ctlr, CPDMA_SOFTRESET, 1);  in cpdma_ctlr_start()
324 	dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);  in cpdma_ctlr_start()
325 	dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);  in cpdma_ctlr_start()
327 	dma_reg_write(ctlr, CPDMA_TXCONTROL, 1);  in cpdma_ctlr_start()
328 	dma_reg_write(ctlr, CPDMA_RXCONTROL, 1);  in cpdma_ctlr_start()
359 	dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);  in cpdma_ctlr_stop()
360 	dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);  in cpdma_ctlr_stop()
362 	dma_reg_write(ctlr, CPDMA_TXCONTROL, 0);  in cpdma_ctlr_stop()
363 	dma_reg_write(ctlr, CPDMA_RXCONTROL, 0);  in cpdma_ctlr_stop()
476 	dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR);  in cpdma_ctlr_int_ctrl()
490 	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value);  in cpdma_ctlr_eoi()
854 	dma_reg_write(ctlr, chan->int_set, chan->mask);  in cpdma_chan_start()
882 	dma_reg_write(ctlr, chan->int_clear, chan->mask);  in cpdma_chan_stop()
885 	dma_reg_write(ctlr, chan->td, chan_linear(chan));  in cpdma_chan_stop()
940 	dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear,  in cpdma_chan_int_ctrl()
1029 	dma_reg_write(ctlr, info->reg, val);  in cpdma_control_set()