2751 struct cas {  struct
2772 	struct cas_init_block *init_block;  argument
2773 	struct cas_tx_desc *init_txds[MAX_TX_RINGS];  argument
2774 	struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS];  argument
2775 	struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS];  argument
2781 	cas_page_t          *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE];  argument
2787 	struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE];  argument
2811 	u32                     cas_flags;  argument
2812 	int                     packet_min; /* minimum packet size */
2813 	int			tx_fifo_size;
2814 	int			rx_fifo_size;
2815 	int			rx_pause_off;
2816 	int			rx_pause_on;
2817 	int                     crc_size;      /* 4 if half-duplex */
2819 	int                     pci_irq_INTC;
2820 	int                     min_frame_size; /* for tx fifo workaround */
2823 	int                     page_size;
2824 	int                     page_order;
2825 	int                     mtu_stride;
2827 	u32			mac_rx_cfg;
2830 	int			link_cntl;
2831 	int			link_fcntl;
2832 	enum link_state		lstate;
2833 	struct timer_list	link_timer;
2834 	int			timer_ticks;
2835 	struct work_struct	reset_task;
2862 	int 			casreg_len; /* reg-space size for dumping */  argument
2863 	u64			pause_entered;
2864 	u16			pause_last_time_recvd;
2866 	dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
2867 	struct pci_dev *pdev;
2868 	struct net_device *dev;
2870 	struct device_node	*of_node;
2874 	u16			fw_load_addr;
2875 	u32			fw_size;
2876 	u8			*fw_data;