Lines Matching refs:readl
378 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV), in cas_entropy_gather()
379 readl(cp->regs + REG_ENTROPY_IV), in cas_entropy_gather()
418 cmd = readl(cp->regs + REG_MIF_FRAME); in cas_phy_read()
440 cmd = readl(cp->regs + REG_MIF_FRAME); in cas_phy_write()
676 cfg = readl(cp->regs + REG_MIF_CFG); in cas_mif_poll()
757 u32 val = readl(cp->regs + REG_PCS_MII_CTRL); in cas_begin_auto_negotiation()
966 val = readl(cp->regs + REG_PCS_MII_CTRL); in cas_phy_init()
973 if ((readl(cp->regs + REG_PCS_MII_CTRL) & in cas_phy_init()
979 readl(cp->regs + REG_PCS_STATE_MACHINE)); in cas_phy_init()
987 val = readl(cp->regs + REG_PCS_MII_ADVERT); in cas_phy_init()
1012 stat = readl(cp->regs + REG_PCS_MII_STATUS); in cas_pcs_link_check()
1014 stat = readl(cp->regs + REG_PCS_MII_STATUS); in cas_pcs_link_check()
1027 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE); in cas_pcs_link_check()
1082 stat = readl(cp->regs + REG_PCS_SERDES_STATE); in cas_pcs_link_check()
1110 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS); in cas_pcs_interrupt()
1120 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS); in cas_txmac_interrupt()
1258 readl(cp->regs + REG_INTR_STATUS_ALIAS); in cas_init_rx_dma()
1262 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i)); in cas_init_rx_dma()
1465 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1477 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1491 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1508 val = readl(cp->regs + REG_RX_CFG);
1511 val = readl(cp->regs + REG_MAC_RX_CFG);
1520 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS); in cas_rxmac_interrupt()
1553 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS); in cas_mac_interrupt()
1692 u32 stat = readl(cp->regs + REG_MIF_STATUS); in cas_mif_interrupt()
1706 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS); in cas_pci_interrupt()
1712 stat, readl(cp->regs + REG_BIM_DIAG)); in cas_pci_interrupt()
1944 limit = readl(cp->regs + REG_TX_COMPN(ring)); in cas_tx()
2299 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]); in cas_rx_ringN()
2416 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry); in cas_post_rxcs_ringN()
2451 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring)); in cas_interruptN()
2502 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); in cas_interrupt1()
2554 u32 status = readl(cp->regs + REG_INTR_STATUS); in cas_interrupt()
2588 u32 status = readl(cp->regs + REG_INTR_STATUS); in cas_poll()
2623 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); in cas_poll()
2631 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2)); in cas_poll()
2639 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3)); in cas_poll()
2691 readl(cp->regs + REG_MIF_STATE_MACHINE)); in cas_tx_timeout()
2694 readl(cp->regs + REG_MAC_STATE_MACHINE)); in cas_tx_timeout()
2697 readl(cp->regs + REG_TX_CFG), in cas_tx_timeout()
2698 readl(cp->regs + REG_MAC_TX_STATUS), in cas_tx_timeout()
2699 readl(cp->regs + REG_MAC_TX_CFG), in cas_tx_timeout()
2700 readl(cp->regs + REG_TX_FIFO_PKT_CNT), in cas_tx_timeout()
2701 readl(cp->regs + REG_TX_FIFO_WRITE_PTR), in cas_tx_timeout()
2702 readl(cp->regs + REG_TX_FIFO_READ_PTR), in cas_tx_timeout()
2703 readl(cp->regs + REG_TX_SM_1), in cas_tx_timeout()
2704 readl(cp->regs + REG_TX_SM_2)); in cas_tx_timeout()
2707 readl(cp->regs + REG_RX_CFG), in cas_tx_timeout()
2708 readl(cp->regs + REG_MAC_RX_STATUS), in cas_tx_timeout()
2709 readl(cp->regs + REG_MAC_RX_CFG)); in cas_tx_timeout()
2712 readl(cp->regs + REG_HP_STATE_MACHINE), in cas_tx_timeout()
2713 readl(cp->regs + REG_HP_STATUS0), in cas_tx_timeout()
2714 readl(cp->regs + REG_HP_STATUS1), in cas_tx_timeout()
2715 readl(cp->regs + REG_HP_STATUS2)); in cas_tx_timeout()
3029 if (readl(cp->regs + REG_MAC_TX_RESET) == 0) in cas_mac_reset()
3037 if (readl(cp->regs + REG_MAC_RX_RESET) == 0) in cas_mac_reset()
3042 if (readl(cp->regs + REG_MAC_TX_RESET) | in cas_mac_reset()
3043 readl(cp->regs + REG_MAC_RX_RESET)) in cas_mac_reset()
3045 readl(cp->regs + REG_MAC_TX_RESET), in cas_mac_reset()
3046 readl(cp->regs + REG_MAC_RX_RESET), in cas_mac_reset()
3047 readl(cp->regs + REG_MAC_STATE_MACHINE)); in cas_mac_reset()
3428 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64; in cas_check_invariants()
3442 cfg = readl(cp->regs + REG_MIF_CFG); in cas_check_invariants()
3467 readl(cp->regs + REG_MIF_STATE_MACHINE)); in cas_check_invariants()
3487 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN; in cas_start_dma()
3489 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN; in cas_start_dma()
3493 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN; in cas_start_dma()
3495 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN; in cas_start_dma()
3500 val = readl(cp->regs + REG_MAC_TX_CFG); in cas_start_dma()
3508 val = readl(cp->regs + REG_MAC_RX_CFG); in cas_start_dma()
3513 readl(cp->regs + REG_MIF_STATE_MACHINE), in cas_start_dma()
3514 readl(cp->regs + REG_MAC_STATE_MACHINE)); in cas_start_dma()
3522 readl(cp->regs + REG_MIF_STATE_MACHINE), in cas_start_dma()
3523 readl(cp->regs + REG_MAC_STATE_MACHINE)); in cas_start_dma()
3544 u32 val = readl(cp->regs + REG_PCS_MII_LPA); in cas_read_pcs_link_mode()
3617 val = readl(cp->regs + REG_PCS_MII_CTRL); in cas_set_link_modes()
3662 val = readl(cp->regs + REG_MAC_RX_CFG); in cas_set_link_modes()
3679 val = readl(cp->regs + REG_MAC_RX_CFG); in cas_set_link_modes()
3707 val = readl(cp->regs + REG_MAC_CTRL_CFG); in cas_set_link_modes()
3774 u32 val = readl(cp->regs + REG_SW_RESET); in cas_global_reset()
3811 val = readl(cp->regs + REG_TX_CFG); in cas_reset()
3815 val = readl(cp->regs + REG_RX_CFG); in cas_reset()
4150 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */ in cas_link_timer()
4160 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) { in cas_link_timer()
4161 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE); in cas_link_timer()
4173 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT); in cas_link_timer()
4174 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR); in cas_link_timer()
4175 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR); in cas_link_timer()
4409 val= readl(cp->regs+ethtool_register_table[i].offsets); in cas_read_regs()
4438 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff; in cas_get_stats()
4440 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff; in cas_get_stats()
4442 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff; in cas_get_stats()
4444 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) + in cas_get_stats()
4445 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff); in cas_get_stats()
4448 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff); in cas_get_stats()
4451 readl(cp->regs + REG_MAC_COLL_EXCESS); in cas_get_stats()
4452 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) + in cas_get_stats()
4453 readl(cp->regs + REG_MAC_COLL_LATE); in cas_get_stats()
4499 rxcfg = readl(cp->regs + REG_MAC_RX_CFG); in cas_set_multicast()
4503 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) { in cas_set_multicast()
4513 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) { in cas_set_multicast()
4588 bmcr = readl(cp->regs + REG_PCS_MII_CTRL); in cas_get_settings()
5123 i = readl(cp->regs + REG_BIM_CFG); in cas_init_one()