Lines Matching refs:value
47 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_tx() local
48 value |= DMA_CONTROL_ST; in dwmac_dma_start_tx()
49 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
54 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx() local
55 value &= ~DMA_CONTROL_ST; in dwmac_dma_stop_tx()
56 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
61 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_rx() local
62 value |= DMA_CONTROL_SR; in dwmac_dma_start_rx()
63 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
68 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx() local
69 value &= ~DMA_CONTROL_SR; in dwmac_dma_stop_rx()
70 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
189 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_dma_interrupt() local
191 if (likely(value & DMA_INTR_ENA_RIE)) { in dwmac_dma_interrupt()
240 u32 value = readl(ioaddr + MAC_CTRL_REG); in stmmac_set_mac() local
243 value |= MAC_RNABLE_RX | MAC_ENABLE_TX; in stmmac_set_mac()
245 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX); in stmmac_set_mac()
247 writel(value, ioaddr + MAC_CTRL_REG); in stmmac_set_mac()