30 void dwmac_enable_dma_transmission(void __iomem *ioaddr)  in dwmac_enable_dma_transmission()  argument
32 	writel(1, ioaddr + DMA_XMT_POLL_DEMAND);  in dwmac_enable_dma_transmission()
35 void dwmac_enable_dma_irq(void __iomem *ioaddr)  in dwmac_enable_dma_irq()  argument
37 	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);  in dwmac_enable_dma_irq()
40 void dwmac_disable_dma_irq(void __iomem *ioaddr)  in dwmac_disable_dma_irq()  argument
42 	writel(0, ioaddr + DMA_INTR_ENA);  in dwmac_disable_dma_irq()
45 void dwmac_dma_start_tx(void __iomem *ioaddr)  in dwmac_dma_start_tx()  argument
47 	u32 value = readl(ioaddr + DMA_CONTROL);  in dwmac_dma_start_tx()
49 	writel(value, ioaddr + DMA_CONTROL);  in dwmac_dma_start_tx()
52 void dwmac_dma_stop_tx(void __iomem *ioaddr)  in dwmac_dma_stop_tx()  argument
54 	u32 value = readl(ioaddr + DMA_CONTROL);  in dwmac_dma_stop_tx()
56 	writel(value, ioaddr + DMA_CONTROL);  in dwmac_dma_stop_tx()
59 void dwmac_dma_start_rx(void __iomem *ioaddr)  in dwmac_dma_start_rx()  argument
61 	u32 value = readl(ioaddr + DMA_CONTROL);  in dwmac_dma_start_rx()
63 	writel(value, ioaddr + DMA_CONTROL);  in dwmac_dma_start_rx()
66 void dwmac_dma_stop_rx(void __iomem *ioaddr)  in dwmac_dma_stop_rx()  argument
68 	u32 value = readl(ioaddr + DMA_CONTROL);  in dwmac_dma_stop_rx()
70 	writel(value, ioaddr + DMA_CONTROL);  in dwmac_dma_stop_rx()
143 int dwmac_dma_interrupt(void __iomem *ioaddr,  in dwmac_dma_interrupt()  argument
148 	u32 intr_status = readl(ioaddr + DMA_STATUS);  in dwmac_dma_interrupt()
189 			u32 value = readl(ioaddr + DMA_INTR_ENA);  in dwmac_dma_interrupt()
209 	writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);  in dwmac_dma_interrupt()
214 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)  in dwmac_dma_flush_tx_fifo()  argument
216 	u32 csr6 = readl(ioaddr + DMA_CONTROL);  in dwmac_dma_flush_tx_fifo()
217 	writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);  in dwmac_dma_flush_tx_fifo()
219 	do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));  in dwmac_dma_flush_tx_fifo()
222 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],  in stmmac_set_mac_addr()  argument
232 	writel(data | GMAC_HI_REG_AE, ioaddr + high);  in stmmac_set_mac_addr()
234 	writel(data, ioaddr + low);  in stmmac_set_mac_addr()
238 void stmmac_set_mac(void __iomem *ioaddr, bool enable)  in stmmac_set_mac()  argument
240 	u32 value = readl(ioaddr + MAC_CTRL_REG);  in stmmac_set_mac()
247 	writel(value, ioaddr + MAC_CTRL_REG);  in stmmac_set_mac()
250 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,  in stmmac_get_mac_addr()  argument
256 	hi_addr = readl(ioaddr + high);  in stmmac_get_mac_addr()
257 	lo_addr = readl(ioaddr + low);  in stmmac_get_mac_addr()