148 	u32 intr_status = readl(ioaddr + DMA_STATUS);  in dwmac_dma_interrupt()  local
152 	pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status);  in dwmac_dma_interrupt()
153 	show_tx_process_state(intr_status);  in dwmac_dma_interrupt()
154 	show_rx_process_state(intr_status);  in dwmac_dma_interrupt()
157 	if (unlikely(intr_status & DMA_STATUS_AIS)) {  in dwmac_dma_interrupt()
158 		if (unlikely(intr_status & DMA_STATUS_UNF)) {  in dwmac_dma_interrupt()
162 		if (unlikely(intr_status & DMA_STATUS_TJT))  in dwmac_dma_interrupt()
165 		if (unlikely(intr_status & DMA_STATUS_OVF))  in dwmac_dma_interrupt()
168 		if (unlikely(intr_status & DMA_STATUS_RU))  in dwmac_dma_interrupt()
170 		if (unlikely(intr_status & DMA_STATUS_RPS))  in dwmac_dma_interrupt()
172 		if (unlikely(intr_status & DMA_STATUS_RWT))  in dwmac_dma_interrupt()
174 		if (unlikely(intr_status & DMA_STATUS_ETI))  in dwmac_dma_interrupt()
176 		if (unlikely(intr_status & DMA_STATUS_TPS)) {  in dwmac_dma_interrupt()
180 		if (unlikely(intr_status & DMA_STATUS_FBI)) {  in dwmac_dma_interrupt()
186 	if (likely(intr_status & DMA_STATUS_NIS)) {  in dwmac_dma_interrupt()
188 		if (likely(intr_status & DMA_STATUS_RI)) {  in dwmac_dma_interrupt()
196 		if (likely(intr_status & DMA_STATUS_TI)) {  in dwmac_dma_interrupt()
200 		if (unlikely(intr_status & DMA_STATUS_ERI))  in dwmac_dma_interrupt()
204 	if (unlikely(intr_status &  in dwmac_dma_interrupt()
206 		pr_warn("%s: unexpected status %08x\n", __func__, intr_status);  in dwmac_dma_interrupt()
209 	writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);  in dwmac_dma_interrupt()