Lines Matching refs:ioaddr
35 static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, in dwmac100_dma_init() argument
38 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac100_dma_init()
43 writel(value, ioaddr + DMA_BUS_MODE); in dwmac100_dma_init()
46 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) in dwmac100_dma_init()
55 ioaddr + DMA_BUS_MODE); in dwmac100_dma_init()
58 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); in dwmac100_dma_init()
63 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); in dwmac100_dma_init()
64 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); in dwmac100_dma_init()
74 static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode, in dwmac100_dma_operation_mode() argument
77 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac100_dma_operation_mode()
86 writel(csr6, ioaddr + DMA_CONTROL); in dwmac100_dma_operation_mode()
89 static void dwmac100_dump_dma_regs(void __iomem *ioaddr) in dwmac100_dump_dma_regs() argument
97 readl(ioaddr + DMA_BUS_MODE + i * 4)); in dwmac100_dump_dma_regs()
100 DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR), in dwmac100_dump_dma_regs()
101 DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR)); in dwmac100_dump_dma_regs()
106 void __iomem *ioaddr) in dwmac100_dma_diagnostic_fr() argument
109 u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR); in dwmac100_dma_diagnostic_fr()