33 static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,  in dwmac1000_dma_init()  argument
36 	u32 value = readl(ioaddr + DMA_BUS_MODE);  in dwmac1000_dma_init()
41 	writel(value, ioaddr + DMA_BUS_MODE);  in dwmac1000_dma_init()
44 		if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))  in dwmac1000_dma_init()
76 	writel(value, ioaddr + DMA_BUS_MODE);  in dwmac1000_dma_init()
95 	writel(burst_len, ioaddr + DMA_AXI_BUS_MODE);  in dwmac1000_dma_init()
98 	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);  in dwmac1000_dma_init()
103 	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);  in dwmac1000_dma_init()
104 	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);  in dwmac1000_dma_init()
130 static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,  in dwmac1000_dma_operation_mode()  argument
133 	u32 csr6 = readl(ioaddr + DMA_CONTROL);  in dwmac1000_dma_operation_mode()
180 	writel(csr6, ioaddr + DMA_CONTROL);  in dwmac1000_dma_operation_mode()
183 static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)  in dwmac1000_dump_dma_regs()  argument
192 			       readl(ioaddr + DMA_BUS_MODE + offset));  in dwmac1000_dump_dma_regs()
197 static unsigned int dwmac1000_get_hw_feature(void __iomem *ioaddr)  in dwmac1000_get_hw_feature()  argument
199 	return readl(ioaddr + DMA_HW_FEATURE);  in dwmac1000_get_hw_feature()
202 static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt)  in dwmac1000_rx_watchdog()  argument
204 	writel(riwt, ioaddr + DMA_RX_WATCHDOG);  in dwmac1000_rx_watchdog()