Lines Matching refs:SMC_REG
481 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
500 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
519 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
536 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
541 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
546 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
572 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
584 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
589 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
590 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
591 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
596 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
601 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
614 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
628 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
633 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
639 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
644 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
647 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
651 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
659 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
664 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
669 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
682 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
683 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
684 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
685 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
690 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
701 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
707 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
714 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
838 #define SMC_REG(lp, reg, bank) \ macro
849 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) macro
870 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
950 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
972 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
990 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \