266 	void __iomem		*port_base;  member
308 static inline void _sc92031_dummy_read(void __iomem *port_base)  in _sc92031_dummy_read()  argument
310 	ioread32(port_base + MAC0);  in _sc92031_dummy_read()
313 static u32 _sc92031_mii_wait(void __iomem *port_base)  in _sc92031_mii_wait()  argument
319 		mii_status = ioread32(port_base + Miistatus);  in _sc92031_mii_wait()
325 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)  in _sc92031_mii_cmd()  argument
327 	iowrite32(Mii_Divider, port_base + Miicmd0);  in _sc92031_mii_cmd()
329 	_sc92031_mii_wait(port_base);  in _sc92031_mii_cmd()
331 	iowrite32(cmd1, port_base + Miicmd1);  in _sc92031_mii_cmd()
332 	iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);  in _sc92031_mii_cmd()
334 	return _sc92031_mii_wait(port_base);  in _sc92031_mii_cmd()
337 static void _sc92031_mii_scan(void __iomem *port_base)  in _sc92031_mii_scan()  argument
339 	_sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);  in _sc92031_mii_scan()
342 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)  in _sc92031_mii_read()  argument
344 	return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;  in _sc92031_mii_read()
347 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)  in _sc92031_mii_write()  argument
349 	_sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));  in _sc92031_mii_write()
355 	void __iomem *port_base = priv->port_base;  in sc92031_disable_interrupts()  local
362 	iowrite32(0, port_base + IntrMask);  in sc92031_disable_interrupts()
363 	_sc92031_dummy_read(port_base);  in sc92031_disable_interrupts()
374 	void __iomem *port_base = priv->port_base;  in sc92031_enable_interrupts()  local
381 	iowrite32(IntrBits, port_base + IntrMask);  in sc92031_enable_interrupts()
388 	void __iomem *port_base = priv->port_base;  in _sc92031_disable_tx_rx()  local
392 	iowrite32(priv->rx_config, port_base + RxConfig);  in _sc92031_disable_tx_rx()
393 	iowrite32(priv->tx_config, port_base + TxConfig);  in _sc92031_disable_tx_rx()
399 	void __iomem *port_base = priv->port_base;  in _sc92031_enable_tx_rx()  local
403 	iowrite32(priv->rx_config, port_base + RxConfig);  in _sc92031_enable_tx_rx()
404 	iowrite32(priv->tx_config, port_base + TxConfig);  in _sc92031_enable_tx_rx()
421 	void __iomem *port_base = priv->port_base;  in _sc92031_set_mar()  local
452 	iowrite32(mar0, port_base + MAR0);  in _sc92031_set_mar()
453 	iowrite32(mar1, port_base + MAR0 + 4);  in _sc92031_set_mar()
459 	void __iomem *port_base = priv->port_base;  in _sc92031_set_rx_config()  local
483 		iowrite32(priv->rx_config, port_base + RxConfig);  in _sc92031_set_rx_config()
489 	void __iomem *port_base = priv->port_base;  in _sc92031_check_media()  local
492 	bmsr = _sc92031_mii_read(port_base, MII_BMSR);  in _sc92031_check_media()
497 		u16 output_status = _sc92031_mii_read(port_base,  in _sc92031_check_media()
499 		_sc92031_mii_scan(port_base);  in _sc92031_check_media()
528 		iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);  in _sc92031_check_media()
539 		_sc92031_mii_scan(port_base);  in _sc92031_check_media()
554 	void __iomem *port_base = priv->port_base;  in _sc92031_phy_reset()  local
557 	phy_ctrl = ioread32(port_base + PhyCtrl);  in _sc92031_phy_reset()
580 	iowrite32(phy_ctrl, port_base + PhyCtrl);  in _sc92031_phy_reset()
584 	iowrite32(phy_ctrl, port_base + PhyCtrl);  in _sc92031_phy_reset()
587 	_sc92031_mii_write(port_base, MII_JAB,  in _sc92031_phy_reset()
589 	_sc92031_mii_scan(port_base);  in _sc92031_phy_reset()
598 	void __iomem *port_base = priv->port_base;  in _sc92031_reset()  local
601 	iowrite32(0, port_base + PMConfig);  in _sc92031_reset()
604 	iowrite32(Cfg0_Reset, port_base + Config0);  in _sc92031_reset()
607 	iowrite32(0, port_base + Config0);  in _sc92031_reset()
611 	iowrite32(0, port_base + IntrMask);  in _sc92031_reset()
614 	iowrite32(0, port_base + MAR0);  in _sc92031_reset()
615 	iowrite32(0, port_base + MAR0 + 4);  in _sc92031_reset()
618 	iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);  in _sc92031_reset()
633 	iowrite32(Cfg1_Rcv64K, port_base + Config1);  in _sc92031_reset()
642 	iowrite32(priv->pm_config, port_base + PMConfig);  in _sc92031_reset()
645 	ioread32(port_base + IntrStatus);  in _sc92031_reset()
651 	void __iomem *port_base = priv->port_base;  in _sc92031_tx_tasklet()  local
660 		tx_status = ioread32(port_base + TxStatus0 + entry * 4);  in _sc92031_tx_tasklet()
724 	void __iomem *port_base = priv->port_base;  in _sc92031_rx_tasklet()  local
731 	rx_ring_head = ioread32(port_base + RxBufWPtr);  in _sc92031_rx_tasklet()
821 	iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);  in _sc92031_rx_tasklet()
838 	void __iomem *port_base = priv->port_base;  in sc92031_tasklet()  local
869 	iowrite32(intr_mask, port_base + IntrMask);  in sc92031_tasklet()
879 	void __iomem *port_base = priv->port_base;  in sc92031_interrupt()  local
883 	iowrite32(0, port_base + IntrMask);  in sc92031_interrupt()
884 	_sc92031_dummy_read(port_base);  in sc92031_interrupt()
886 	intr_status = ioread32(port_base + IntrStatus);  in sc92031_interrupt()
903 	iowrite32(intr_mask, port_base + IntrMask);  in sc92031_interrupt()
912 	void __iomem *port_base = priv->port_base;  in sc92031_get_stats()  local
921 		temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;  in sc92031_get_stats()
939 	void __iomem *port_base = priv->port_base;  in sc92031_start_xmit()  local
979 			port_base + TxAddr0 + entry * 4);  in sc92031_start_xmit()
980 	iowrite32(tx_status, port_base + TxStatus0 + entry * 4);  in sc92031_start_xmit()
1129 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_get_settings()  local
1136 	phy_address = ioread32(port_base + Miicmd1) >> 27;  in sc92031_ethtool_get_settings()
1137 	phy_ctrl = ioread32(port_base + PhyCtrl);  in sc92031_ethtool_get_settings()
1139 	output_status = _sc92031_mii_read(port_base, MII_OutputStatus);  in sc92031_ethtool_get_settings()
1140 	_sc92031_mii_scan(port_base);  in sc92031_ethtool_get_settings()
1187 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_set_settings()  local
1241 	old_phy_ctrl = ioread32(port_base + PhyCtrl);  in sc92031_ethtool_set_settings()
1245 		iowrite32(phy_ctrl, port_base + PhyCtrl);  in sc92031_ethtool_set_settings()
1256 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_get_wol()  local
1260 	pm_config = ioread32(port_base + PMConfig);  in sc92031_ethtool_get_wol()
1283 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_set_wol()  local
1288 	pm_config = ioread32(port_base + PMConfig)  in sc92031_ethtool_set_wol()
1302 	iowrite32(pm_config, port_base + PMConfig);  in sc92031_ethtool_set_wol()
1314 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_nway_reset()  local
1319 	bmcr = _sc92031_mii_read(port_base, MII_BMCR);  in sc92031_ethtool_nway_reset()
1325 	_sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);  in sc92031_ethtool_nway_reset()
1328 	_sc92031_mii_scan(port_base);  in sc92031_ethtool_nway_reset()
1401 	void __iomem* port_base;  in sc92031_probe()  local
1424 	port_base = pci_iomap(pdev, SC92031_USE_PIO, 0);  in sc92031_probe()
1425 	if (unlikely(!port_base)) {  in sc92031_probe()
1449 	priv->port_base = port_base;  in sc92031_probe()
1457 	iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);  in sc92031_probe()
1459 	mac0 = ioread32(port_base + MAC0);  in sc92031_probe()
1460 	mac1 = ioread32(port_base + MAC0 + 4);  in sc92031_probe()
1481 	pci_iounmap(pdev, port_base);  in sc92031_probe()
1495 	void __iomem* port_base = priv->port_base;  in sc92031_remove()  local
1499 	pci_iounmap(pdev, port_base);  in sc92031_remove()