Lines Matching refs:BIT
117 #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 cor…
118 #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
119 #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loo…
121 #define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */
122 #define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */
132 #define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link…
155 #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
156 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
157 #define METH_DMA_RX_EN BIT(15) /* Enable RX */
158 #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
167 #define METH_RX_ST_VALID BIT(63)
168 #define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
169 #define METH_RX_ST_DRBL_NBL BIT(17)
170 #define METH_RX_ST_CRC_ERR BIT(18)
171 #define METH_RX_ST_MCAST_PKT BIT(19)
172 #define METH_RX_ST_BCAST_PKT BIT(20)
173 #define METH_RX_ST_INV_PREAMBLE_CTX BIT(21)
174 #define METH_RX_ST_LONG_EVT_SEEN BIT(22)
175 #define METH_RX_ST_BAD_PACKET BIT(23)
176 #define METH_RX_ST_CARRIER_EVT_SEEN BIT(24)
177 #define METH_RX_ST_MCAST_FILTER_MATCH BIT(25)
178 #define METH_RX_ST_PHYS_ADDR_MATCH BIT(26)
191 #define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */
192 #define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */
194 #define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure…
195 #define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */
197 #define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stop…
198 #define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold cond…
199 #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could no…
200 #define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped,…
219 #define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latche…
222 #define METH_TX_ST_DONE BIT(63) /* TX complete */
223 #define METH_TX_ST_SUCCESS BIT(23) /* Packet was transmitted successfully */
224 #define METH_TX_ST_TOOLONG BIT(24) /* TX abort due to excessive length */
225 #define METH_TX_ST_UNDERRUN BIT(25) /* TX abort due to underrun (?) */
226 #define METH_TX_ST_EXCCOLL BIT(26) /* TX abort due to excess collisions */
227 #define METH_TX_ST_DEFER BIT(27) /* TX abort due to excess deferals */
228 #define METH_TX_ST_LATECOLL BIT(28) /* TX abort due to late collision */
232 #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
235 #define MDIO_BUSY BIT(16)