333 	EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);  in falcon_setsda()
343 	EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);  in falcon_setscl()
989 	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);  in falcon_setup_xaui()
990 	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);  in falcon_setup_xaui()
991 	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);  in falcon_setup_xaui()
992 	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);  in falcon_setup_xaui()
993 	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);  in falcon_setup_xaui()
994 	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);  in falcon_setup_xaui()
995 	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);  in falcon_setup_xaui()
996 	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);  in falcon_setup_xaui()
1074 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);  in falcon_xgxs_link_ok()
1075 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);  in falcon_xgxs_link_ok()
1076 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);  in falcon_xgxs_link_ok()
1175 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,  in falcon_reconfigure_xgxs_core()
1178 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);  in falcon_reconfigure_xgxs_core()
1179 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);  in falcon_reconfigure_xgxs_core()
1183 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);  in falcon_reconfigure_xgxs_core()
1184 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);  in falcon_reconfigure_xgxs_core()
1185 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);  in falcon_reconfigure_xgxs_core()
1186 	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);  in falcon_reconfigure_xgxs_core()
1297 	EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);  in falcon_reset_macs()
1301 	EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);  in falcon_reset_macs()
1302 	EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);  in falcon_reset_macs()
1303 	EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);  in falcon_reset_macs()
1357 	EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);  in falcon_deconfigure_mac_wrapper()
1392 		EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,  in falcon_reconfigure_mac_wrapper()
1404 	EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);  in falcon_reconfigure_mac_wrapper()
1407 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);  in falcon_reconfigure_mac_wrapper()
2115 	EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);  in falcon_reset_sram()
2116 	EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);  in falcon_reset_sram()
2435 		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);  in falcon_init_rx_cfg()
2436 		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,  in falcon_init_rx_cfg()
2438 		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);  in falcon_init_rx_cfg()
2439 		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);  in falcon_init_rx_cfg()
2440 		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);  in falcon_init_rx_cfg()
2441 		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);  in falcon_init_rx_cfg()
2444 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);  in falcon_init_rx_cfg()
2445 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,  in falcon_init_rx_cfg()
2448 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);  in falcon_init_rx_cfg()
2449 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);  in falcon_init_rx_cfg()
2450 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);  in falcon_init_rx_cfg()
2451 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);  in falcon_init_rx_cfg()
2452 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);  in falcon_init_rx_cfg()
2457 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);  in falcon_init_rx_cfg()
2458 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);  in falcon_init_rx_cfg()
2459 		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);  in falcon_init_rx_cfg()
2463 	EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);  in falcon_init_rx_cfg()
2478 	EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);  in falcon_init_nic()
2490 		EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);  in falcon_init_nic()
2496 		EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);  in falcon_init_nic()
2497 		EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);  in falcon_init_nic()
2498 		EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);  in falcon_init_nic()
2499 		EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);  in falcon_init_nic()
2508 	EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);  in falcon_init_nic()
2509 	EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);  in falcon_init_nic()
2511 		EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);  in falcon_init_nic()
2518 	EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);  in falcon_init_nic()