Lines Matching refs:BIT
202 #define SXGBE_CORE_RSS_CTL_UDP4TE BIT(3)
203 #define SXGBE_CORE_RSS_CTL_TCP4TE BIT(2)
204 #define SXGBE_CORE_RSS_CTL_IP2TE BIT(1)
205 #define SXGBE_CORE_RSS_CTL_RSSE BIT(0)
266 #define SXGBE_MTL_SFMODE BIT(1)
281 #define SXGBE_RX_MTL_SFMODE BIT(5)
298 #define SXGBE_DMA_SOFT_RESET BIT(0)
300 #define SXGBE_DMA_AXI_UNDEF_BURST BIT(0)
301 #define SXGBE_DMA_ENHACE_ADDR_MODE BIT(11)
317 #define SXGBE_DMA_PBL_X8MODE BIT(16)
318 #define SXGBE_DMA_CHA_TXCTL_TSE_ENABLE BIT(12)
359 #define SXGBE_TX_START_DMA BIT(0)
367 #define SXGBE_TX_ENABLE BIT(0)
368 #define SXGBE_TX_DISDIC_ALGO BIT(1)
369 #define SXGBE_TX_JABBER_DISABLE BIT(16)
372 #define SXGBE_RX_ENABLE BIT(0)
373 #define SXGBE_RX_ACS_ENABLE BIT(1)
374 #define SXGBE_RX_WATCHDOG_DISABLE BIT(7)
375 #define SXGBE_RX_JUMBPKT_ENABLE BIT(8)
376 #define SXGBE_RX_CSUMOFFLOAD_ENABLE BIT(9)
377 #define SXGBE_RX_LOOPBACK_ENABLE BIT(10)
378 #define SXGBE_RX_ARPOFFLOAD_ENABLE BIT(31)
381 #define SXGBE_VLAN_SVLAN_ENABLE BIT(18)
382 #define SXGBE_VLAN_DOUBLEVLAN_ENABLE BIT(26)
383 #define SXGBE_VLAN_INNERVLAN_ENABLE BIT(27)
395 #define SXGBE_VLAN_PRTY_CTL BIT(18)
396 #define SXGBE_VLAN_CSVL_CTL BIT(19)
399 #define SXGBE_TX_FLOW_CTL_FCB BIT(0)
400 #define SXGBE_TX_FLOW_CTL_TFB BIT(1)
403 #define SXGBE_RX_FLOW_CTL_ENABLE BIT(0)
404 #define SXGBE_RX_UNICAST_DETECT BIT(1)
405 #define SXGBE_RX_PRTYFLOW_CTL_ENABLE BIT(8)
449 #define SXGBE_DMA_INT_ENA_NIE BIT(16) /* Normal Summary */
450 #define SXGBE_DMA_INT_ENA_TIE BIT(0) /* Transmit Interrupt */
451 #define SXGBE_DMA_INT_ENA_TUE BIT(2) /* Transmit Buffer Unavailable */
452 #define SXGBE_DMA_INT_ENA_RIE BIT(6) /* Receive Interrupt */
459 #define SXGBE_DMA_INT_ENA_AIE BIT(15) /* Abnormal Summary */
460 #define SXGBE_DMA_INT_ENA_TSE BIT(1) /* Transmit Stopped */
461 #define SXGBE_DMA_INT_ENA_RUE BIT(7) /* Receive Buffer Unavailable */
462 #define SXGBE_DMA_INT_ENA_RSE BIT(8) /* Receive Stopped */
463 #define SXGBE_DMA_INT_ENA_FBE BIT(12) /* Fatal Bus Error */
464 #define SXGBE_DMA_INT_ENA_CDEE BIT(13) /* Context Descriptor Error */
474 #define SXGBE_DMA_INT_STATUS_REB2 BIT(21)
475 #define SXGBE_DMA_INT_STATUS_REB1 BIT(20)
476 #define SXGBE_DMA_INT_STATUS_REB0 BIT(19)
477 #define SXGBE_DMA_INT_STATUS_TEB2 BIT(18)
478 #define SXGBE_DMA_INT_STATUS_TEB1 BIT(17)
479 #define SXGBE_DMA_INT_STATUS_TEB0 BIT(16)
480 #define SXGBE_DMA_INT_STATUS_NIS BIT(15)
481 #define SXGBE_DMA_INT_STATUS_AIS BIT(14)
482 #define SXGBE_DMA_INT_STATUS_CTXTERR BIT(13)
483 #define SXGBE_DMA_INT_STATUS_FBE BIT(12)
484 #define SXGBE_DMA_INT_STATUS_RPS BIT(8)
485 #define SXGBE_DMA_INT_STATUS_RBU BIT(7)
486 #define SXGBE_DMA_INT_STATUS_RI BIT(6)
487 #define SXGBE_DMA_INT_STATUS_TBU BIT(2)
488 #define SXGBE_DMA_INT_STATUS_TPS BIT(1)
489 #define SXGBE_DMA_INT_STATUS_TI BIT(0)