Lines Matching refs:readl
28 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
53 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
59 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
63 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
103 tx_config = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_enable_dma_transmission()
127 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_start_tx()
138 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_start_tx_queue()
147 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_stop_tx_queue()
158 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_stop_tx()
170 rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_start_rx()
183 rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_stop_rx()
192 u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_tx_dma_int_status()
264 u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_rx_dma_int_status()
342 ctrl = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num)); in sxgbe_enable_tso()