Lines Matching refs:clear_val
193 u32 clear_val = 0; in sxgbe_tx_dma_int_status() local
202 clear_val |= SXGBE_DMA_INT_STATUS_TI; in sxgbe_tx_dma_int_status()
208 clear_val |= SXGBE_DMA_INT_STATUS_TBU; in sxgbe_tx_dma_int_status()
214 clear_val |= SXGBE_DMA_INT_STATUS_TPS; in sxgbe_tx_dma_int_status()
230 clear_val |= SXGBE_DMA_INT_STATUS_TEB0; in sxgbe_tx_dma_int_status()
237 clear_val |= SXGBE_DMA_INT_STATUS_TEB1; in sxgbe_tx_dma_int_status()
244 clear_val |= SXGBE_DMA_INT_STATUS_TEB2; in sxgbe_tx_dma_int_status()
251 clear_val |= SXGBE_DMA_INT_STATUS_CTXTERR; in sxgbe_tx_dma_int_status()
256 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_tx_dma_int_status()
265 u32 clear_val = 0; in sxgbe_rx_dma_int_status() local
274 clear_val |= SXGBE_DMA_INT_STATUS_RI; in sxgbe_rx_dma_int_status()
280 clear_val |= SXGBE_DMA_INT_STATUS_RBU; in sxgbe_rx_dma_int_status()
286 clear_val |= SXGBE_DMA_INT_STATUS_RPS; in sxgbe_rx_dma_int_status()
302 clear_val |= SXGBE_DMA_INT_STATUS_REB0; in sxgbe_rx_dma_int_status()
309 clear_val |= SXGBE_DMA_INT_STATUS_REB1; in sxgbe_rx_dma_int_status()
316 clear_val |= SXGBE_DMA_INT_STATUS_REB2; in sxgbe_rx_dma_int_status()
322 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_rx_dma_int_status()