Lines Matching refs:sh_eth_write
409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) in sh_eth_write() function
463 sh_eth_write(ndev, value, RMII_MII); in sh_eth_select_mii()
471 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); in sh_eth_set_duplex()
473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); in sh_eth_set_duplex()
483 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR); in sh_eth_set_rate_r8a777x()
486 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR); in sh_eth_set_rate_r8a777x()
548 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); in sh_eth_set_rate_sh7724()
551 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); in sh_eth_set_rate_sh7724()
588 sh_eth_write(ndev, 0, RTRATE); in sh_eth_set_rate_sh7757()
591 sh_eth_write(ndev, 1, RTRATE); in sh_eth_set_rate_sh7757()
654 sh_eth_write(ndev, 0x00000000, GECMR); in sh_eth_set_rate_giga()
657 sh_eth_write(ndev, 0x00000010, GECMR); in sh_eth_set_rate_giga()
660 sh_eth_write(ndev, 0x00000020, GECMR); in sh_eth_set_rate_giga()
713 sh_eth_write(ndev, GECMR_10, GECMR); in sh_eth_set_rate_gether()
716 sh_eth_write(ndev, GECMR_100, GECMR); in sh_eth_set_rate_gether()
719 sh_eth_write(ndev, GECMR_1000, GECMR); in sh_eth_set_rate_gether()
924 sh_eth_write(ndev, EDSR_ENALL, EDSR); in sh_eth_reset()
925 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, in sh_eth_reset()
933 sh_eth_write(ndev, 0x0, TDLAR); in sh_eth_reset()
934 sh_eth_write(ndev, 0x0, TDFAR); in sh_eth_reset()
935 sh_eth_write(ndev, 0x0, TDFXR); in sh_eth_reset()
936 sh_eth_write(ndev, 0x0, TDFFR); in sh_eth_reset()
937 sh_eth_write(ndev, 0x0, RDLAR); in sh_eth_reset()
938 sh_eth_write(ndev, 0x0, RDFAR); in sh_eth_reset()
939 sh_eth_write(ndev, 0x0, RDFXR); in sh_eth_reset()
940 sh_eth_write(ndev, 0x0, RDFFR); in sh_eth_reset()
944 sh_eth_write(ndev, 0x0, CSMR); in sh_eth_reset()
950 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, in sh_eth_reset()
953 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, in sh_eth_reset()
995 sh_eth_write(ndev, in update_mac_address()
998 sh_eth_write(ndev, in update_mac_address()
1206 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); in sh_eth_ring_format()
1209 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); in sh_eth_ring_format()
1229 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); in sh_eth_ring_format()
1232 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); in sh_eth_ring_format()
1302 sh_eth_write(ndev, 0x1, RMIIMODE); in sh_eth_dev_init()
1307 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); in sh_eth_dev_init()
1310 sh_eth_write(ndev, 0, EESIPR); in sh_eth_dev_init()
1314 sh_eth_write(ndev, EDMR_EL, EDMR); in sh_eth_dev_init()
1317 sh_eth_write(ndev, 0, EDMR); in sh_eth_dev_init()
1320 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); in sh_eth_dev_init()
1321 sh_eth_write(ndev, 0, TFTR); in sh_eth_dev_init()
1324 sh_eth_write(ndev, RMCR_RNC, RMCR); in sh_eth_dev_init()
1326 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); in sh_eth_dev_init()
1329 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ in sh_eth_dev_init()
1331 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); in sh_eth_dev_init()
1334 sh_eth_write(ndev, 0, TRIMD); in sh_eth_dev_init()
1337 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, in sh_eth_dev_init()
1340 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); in sh_eth_dev_init()
1343 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); in sh_eth_dev_init()
1350 sh_eth_write(ndev, val, ECMR); in sh_eth_dev_init()
1356 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); in sh_eth_dev_init()
1360 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); in sh_eth_dev_init()
1367 sh_eth_write(ndev, APR_AP, APR); in sh_eth_dev_init()
1369 sh_eth_write(ndev, MPR_MP, MPR); in sh_eth_dev_init()
1371 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); in sh_eth_dev_init()
1375 sh_eth_write(ndev, EDRRR_R, EDRRR); in sh_eth_dev_init()
1398 sh_eth_write(ndev, 0, EDRRR); in sh_eth_dev_exit()
1580 sh_eth_write(ndev, EDRRR_R, EDRRR); in sh_eth_rx()
1591 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & in sh_eth_rcv_snd_disable()
1598 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | in sh_eth_rcv_snd_enable()
1612 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ in sh_eth_error()
1628 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & in sh_eth_error()
1631 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), in sh_eth_error()
1633 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | in sh_eth_error()
1703 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); in sh_eth_error()
1735 sh_eth_write(ndev, 0, EESIPR); in sh_eth_interrupt()
1742 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, in sh_eth_interrupt()
1755 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); in sh_eth_interrupt()
1763 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); in sh_eth_interrupt()
1787 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); in sh_eth_poll()
1797 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); in sh_eth_poll()
1824 sh_eth_write(ndev, in sh_eth_adjust_link()
2250 sh_eth_write(ndev, 0x0000, EESIPR); in sh_eth_set_ringparam()
2277 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); in sh_eth_set_ringparam()
2279 sh_eth_write(ndev, EDRRR_R, EDRRR); in sh_eth_set_ringparam()
2426 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); in sh_eth_start_xmit()
2443 sh_eth_write(ndev, 0, reg); in sh_eth_update_stat()
2488 sh_eth_write(ndev, 0x0000, EESIPR); in sh_eth_close()
2804 sh_eth_write(ndev, ecmr_bits, ECMR); in sh_eth_set_rx_mode()
3199 sh_eth_write(ndev, 0x1, RMIIMODE); in sh_eth_drv_probe()