60 	ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,  in ravb_config()
79 	ravb_write(ndev, ecmr, ECMR);  in ravb_set_duplex()
88 		ravb_write(ndev, GECMR_SPEED_100, GECMR);  in ravb_set_rate()
91 		ravb_write(ndev, GECMR_SPEED_1000, GECMR);  in ravb_set_rate()
135 	ravb_write(priv->ndev, pir, PIR);  in ravb_mdio_ctrl()
344 	ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);  in ravb_emac_init()
350 	ravb_write(ndev, ecmr, ECMR);  in ravb_emac_init()
355 	ravb_write(ndev,  in ravb_emac_init()
358 	ravb_write(ndev,  in ravb_emac_init()
361 	ravb_write(ndev, 1, MPR);  in ravb_emac_init()
364 	ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);  in ravb_emac_init()
367 	ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);  in ravb_emac_init()
394 	ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC);  in ravb_dmac_init()
396 	ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC);  in ravb_dmac_init()
400 	ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);  in ravb_dmac_init()
403 	ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);  in ravb_dmac_init()
406 	ravb_write(ndev, TCCR_TFEN, TCCR);  in ravb_dmac_init()
410 	ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);  in ravb_dmac_init()
412 	ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);  in ravb_dmac_init()
414 	ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);  in ravb_dmac_init()
417 	ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION,  in ravb_dmac_init()
492 		ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR);  in ravb_get_tx_tstamp()
612 	ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR);  in ravb_rcv_snd_disable()
618 	ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR);  in ravb_rcv_snd_enable()
656 	ravb_write(ndev, ecsr, ECSR);	/* clear interrupt */  in ravb_emac_interrupt()
683 	ravb_write(ndev, ~EIS_QFS, EIS);  in ravb_error_interrupt()
686 		ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);  in ravb_error_interrupt()
723 			ravb_write(ndev, ~TIS_TFUF, TIS);  in ravb_interrupt()
736 					ravb_write(ndev, ric0, RIC0);  in ravb_interrupt()
737 					ravb_write(ndev, tic, TIC);  in ravb_interrupt()
791 			ravb_write(ndev, ~mask, RIS0);  in ravb_poll()
799 			ravb_write(ndev, ~mask, TIS);  in ravb_poll()
811 	ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0);  in ravb_poll()
812 	ravb_write(ndev, ravb_read(ndev, TIC)  | mask,  TIC);  in ravb_poll()
851 			ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF,  in ravb_adjust_link()
1379 	ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);  in ravb_start_xmit()
1419 	ravb_write(ndev, 0, TROCR);	/* (write clear) */  in ravb_get_stats()
1421 	ravb_write(ndev, 0, CDCR);	/* (write clear) */  in ravb_get_stats()
1423 	ravb_write(ndev, 0, LCCR);	/* (write clear) */  in ravb_get_stats()
1426 	ravb_write(ndev, 0, CERCR);	/* (write clear) */  in ravb_get_stats()
1428 	ravb_write(ndev, 0, CEECR);	/* (write clear) */  in ravb_get_stats()
1462 	ravb_write(ndev, ecmr, ECMR);  in ravb_set_rx_mode()
1476 	ravb_write(ndev, 0, RIC0);  in ravb_close()
1477 	ravb_write(ndev, 0, RIC1);  in ravb_close()
1478 	ravb_write(ndev, 0, RIC2);  in ravb_close()
1479 	ravb_write(ndev, 0, TIC);  in ravb_close()
1755 	ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,  in ravb_probe()
1759 	ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB,  in ravb_probe()
1763 	ravb_write(ndev, ((1000 << 20) / 130) & GTI_TIV, GTI);  in ravb_probe()
1766 	ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR);  in ravb_probe()
1781 	ravb_write(ndev, priv->desc_bat_dma, DBAT);  in ravb_probe()
1844 	ravb_write(ndev, CCC_OPC_RESET, CCC);  in ravb_remove()