107 #define RTL_R32(reg)		readl (ioaddr + (reg))  macro
980 	return RTL_R32(GPHY_OCP) & OCPAR_FLAG;  in DECLARE_RTL_COND()
1005 		(RTL_R32(GPHY_OCP) & 0xffff) : ~0;  in r8168_phy_ocp_read()
1027 	return RTL_R32(OCPDR);  in r8168_mac_ocp_read()
1072 	return RTL_R32(PHYAR) & 0x80000000;  in DECLARE_RTL_COND()
1097 		RTL_R32(PHYAR) & 0xffff : ~0;  in r8169_mdio_read()
1112 	return RTL_R32(OCPAR) & OCPAR_FLAG;  in DECLARE_RTL_COND()
1143 		RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;  in r8168dp_1_mdio_read()
1150 	RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_start()
1155 	RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_stop()
1225 	return RTL_R32(EPHYAR) & EPHYAR_FLAG;  in DECLARE_RTL_COND()
1247 		RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;  in rtl_ephy_read()
1254 	return RTL_R32(ERIAR) & ERIAR_FLAG;  in DECLARE_RTL_COND()
1276 		RTL_R32(ERIDR) : ~0;  in rtl_eri_read()
1294 		RTL_R32(OCPDR) : ~0;  in r8168dp_ocp_read()
1514 	return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;  in DECLARE_RTL_COND()
1524 		RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;  in rtl8168d_efuse_read()
1579 	return RTL_R32(TBICSR) & TBIReset;  in rtl8169_tbi_reset_pending()
1589 	return RTL_R32(TBICSR) & TBILinkOk;  in rtl8169_tbi_link_ok()
1601 	RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);  in rtl8169_tbi_reset_enable()
1897 	reg = RTL_R32(TBICSR);  in rtl8169_set_speed_tbi()
2046 	rx_config = RTL_R32(RxConfig);  in __rtl8169_set_features()
2111 	status = RTL_R32(TBICSR);  in rtl8169_gset_tbi()
2198 	return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);  in DECLARE_RTL_COND()
2452 	reg = RTL_R32(TxConfig);  in rtl8169_get_mac_version()
4444 	RTL_R32(MAC4);  in rtl_rar_set()
4447 	RTL_R32(MAC0);  in rtl_rar_set()
4599 		RTL_W32(RxConfig, RTL_R32(RxConfig) |  in rtl_wol_suspend_quirk()
5190 	RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);  in rtl_rx_close()
5204 	return RTL_R32(TxConfig) & TXCFG_EMPTY;  in DECLARE_RTL_COND()
5354 	tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;  in rtl_set_rx_mode()
5477 	return RTL_R32(CSIAR) & CSIAR_FLAG;  in DECLARE_RTL_COND()
5499 		RTL_R32(CSIDR) : ~0;  in r8169_csi_read()
5522 		RTL_R32(CSIDR) : ~0;  in r8402_csi_read()
5545 		RTL_R32(CSIDR) : ~0;  in r8411_csi_read()
5876 	RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);  in rtl_hw_start_8168e_1()
5877 	RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);  in rtl_hw_start_8168e_1()
5911 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168e_2()
5918 	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);  in rtl_hw_start_8168e_2()
5946 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168f()
5949 	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);  in rtl_hw_start_8168f()
5995 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168g()
6010 	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168g()
6100 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168h_1()
6120 	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168h_1()
6185 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168ep()
6203 	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168ep()
6514 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);  in rtl_hw_start_8105e_1()
6517 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);  in rtl_hw_start_8105e_1()
6544 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);  in rtl_hw_start_8402()
6546 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8402()
6569 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);  in rtl_hw_start_8106()
6571 	RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);  in rtl_hw_start_8106()
7579 	dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);  in rtl8169_rx_missed()
8095 	RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);  in rtl_hw_init_8168g()
8426 		   (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);  in rtl_init_one()